[Bug target/61665] New: aarch64: instruction ordering problem when using vector register for integer math

Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: janne-gcc at jannau dot net Created attachment 33041 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=33041&action=edit preprocessed source One of libav

[Bug target/63277] New: ARM - NEON excessive use of vmov for vtbl2 / uint8x8x2 for shuffling data unnecessarily around

Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: janne-gcc at jannau dot net Created attachment 33500 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=33500&action=edit small example source code

[Bug target/63277] ARM - NEON excessive use of vmov for vtbl2 / uint8x8x2 for shuffling data unnecessarily around

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63277 --- Comment #3 from Janne Grunau --- Created attachment 33501 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=33501&action=edit arm_neon_excessive_vmov_wo_vcombine.c

[Bug target/63277] ARM - NEON excessive use of vmov for vtbl2 / uint8x8x2 for shuffling data unnecessarily around

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63277 --- Comment #2 from Janne Grunau --- It is not only the vcombine. The handling of the table vectors is even more dreadful. The loads are combined to properly paired registers. Then moved in reverse in order to different registers to be assembled