[Bug target/114264] New: RISC-V: ICE in riscv-vector-costs.cc of gcc master branch

2024-03-07 Thread deminhan at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114264 Bug ID: 114264 Summary: RISC-V: ICE in riscv-vector-costs.cc of gcc master branch Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal

[Bug target/114506] New: RISC-V: expect M8 but M4 generated with dynamic LMUL

2024-03-27 Thread deminhan at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114506 Bug ID: 114506 Summary: RISC-V: expect M8 but M4 generated with dynamic LMUL Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal Priority: P3 Com

[Bug target/114516] New: RISC-V: TSVC2 s315 has spill with dynamic lmul

2024-03-28 Thread deminhan at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114516 Bug ID: 114516 Summary: RISC-V: TSVC2 s315 has spill with dynamic lmul Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal Priority: P3 Component

[Bug target/116564] New: aarch64: gcc can't finish when compiling vst2_f64 instrinsic with opt level >= O1

2024-09-02 Thread deminhan at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116564 Bug ID: 116564 Summary: aarch64: gcc can't finish when compiling vst2_f64 instrinsic with opt level >= O1 Product: gcc Version: 15.0 Status: UNCONFIRMED Severi

[Bug c/114887] New: RISC-V: expect M8 but M4 generated with dynamic LMUL for TSVC s319

2024-04-29 Thread deminhan at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114887 Bug ID: 114887 Summary: RISC-V: expect M8 but M4 generated with dynamic LMUL for TSVC s319 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug c++/115061] New: Compiling gcc failed when using clang 16.0.6

2024-05-12 Thread deminhan at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115061 Bug ID: 115061 Summary: Compiling gcc failed when using clang 16.0.6 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c++

[Bug target/115759] New: RISC-V: complex code generated for lmbench's fwr when uses scalable autovec

2024-07-02 Thread deminhan at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115759 Bug ID: 115759 Summary: RISC-V: complex code generated for lmbench's fwr when uses scalable autovec Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: no

[Bug other/117893] New: gcc configure failed

2024-12-03 Thread deminhan at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117893 Bug ID: 117893 Summary: gcc configure failed Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: other Assignee: u

[Bug target/112092] RISC-V: Suboptimal RVV code produced for vsetvl-11.c and vsetvlmax-8.c

2024-12-05 Thread deminhan at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112092 Demin Han changed: What|Removed |Added CC||deminhan at gcc dot gnu.org --- Comment #13

[Bug target/112092] RISC-V: Suboptimal RVV code produced for vsetvl-11.c and vsetvlmax-8.c

2024-12-05 Thread deminhan at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112092 --- Comment #15 from Demin Han --- (In reply to Maciej W. Rozycki from comment #14) > This is invalid code, because you haven't told GCC your inline assembly > makes use of v8 or v24. You need to specify inputs and outputs correctly > or otherw