[Bug target/113035] RISC-V: regression testsuite errors -mtune=sifive-7-series

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113035 Dusan Stojkovic changed: What|Removed |Added CC||dusan.stojko...@rt-rk.com --- Comment

[Bug target/113035] RISC-V: regression testsuite errors -mtune=sifive-7-series

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113035 --- Comment #3 from Dusan Stojkovic --- Upon further investigation into the bug related to the vsetvl-*.c tests (specifically vsetvl-13.c, vsetvl-15.c, and vsetvl-23.c), we found the following: When using the mtune=sifive-7-series tuning, tests

[Bug target/116425] RISC-V missed optimization: vector lowering along lmul boundaries

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116425 Dusan Stojkovic changed: What|Removed |Added CC||dusan.stojko...@rt-rk.com --- Comment

[Bug tree-optimization/116766] New: Missed loop vectorization case with gather/scatter

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116766 Bug ID: 116766 Summary: Missed loop vectorization case with gather/scatter Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Componen

[Bug tree-optimization/119253] New: RISC-V GCC auto-vectorizes unaligned memory access even if mvector-strict-align is enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119253 Bug ID: 119253 Summary: RISC-V GCC auto-vectorizes unaligned memory access even if mvector-strict-align is enabled Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug tree-optimization/119253] RISC-V GCC auto-vectorizes unaligned memory access even if mvector-strict-align is enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119253 Dusan Stojkovic changed: What|Removed |Added Resolution|INVALID |FIXED --- Comment #2 from Dusan Stojk