https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #21 from JuzheZhong ---
Hi, Richi.
Finish and confirm RISC-V regression.
All pass.
Thank you so much!
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #20 from CVS Commits ---
The trunk branch has been updated by Lehua Ding :
https://gcc.gnu.org/g:5255273ee8b14ea565eb43f067a86370d25df114
commit r14-4538-g5255273ee8b14ea565eb43f067a86370d25df114
Author: Juzhe-Zhong
Date: Tue Oc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #19 from CVS Commits ---
The master branch has been updated by Richard Biener :
https://gcc.gnu.org/g:70b5c6981fcdff246f90e57e91f3e1667eab2eb3
commit r14-4537-g70b5c6981fcdff246f90e57e91f3e1667eab2eb3
Author: Richard Biener
Date:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #18 from JuzheZhong ---
(In reply to Richard Biener from comment #16)
> (In reply to JuzheZhong from comment #14)
> > Also this case ICE:
> >
> > typedef unsigned char __attribute__((vector_size(4))) uvec;
> >
> > int main (int arg
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #17 from CVS Commits ---
The trunk branch has been updated by Lehua Ding :
https://gcc.gnu.org/g:a704603d458b1e55b561ddfb4e513581ee863ed6
commit r14-4528-ga704603d458b1e55b561ddfb4e513581ee863ed6
Author: Juzhe-Zhong
Date: Tue Oc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #16 from Richard Biener ---
(In reply to JuzheZhong from comment #14)
> Also this case ICE:
>
> typedef unsigned char __attribute__((vector_size(4))) uvec;
>
> int main (int argc, char *argv[]) {
> int i;
> int x = 0;
>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #15 from JuzheZhong ---
Also, I find this following case that ARM SVE failed to optimize:
https://godbolt.org/z/d6YnneETj
#define N 16
typedef int half_word;
int foo2 ()
{
int i;
half_word ia[N];
half_word ic[N] = {0,3,6,9,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #14 from JuzheZhong ---
Also this case ICE:
typedef unsigned char __attribute__((vector_size(4))) uvec;
int main (int argc, char *argv[]) {
int i;
int x = 0;
uvec uc0 = (uvec) {argc, 1, 2, 10};
unsigned char uc1[4
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #13 from JuzheZhong ---
Thanks, Richi.
It does fix this issue.
This patch seems to cause an ICE in RISC-V:
#include
#include
#define N 128
int
main ()
{
uint8_t mask[N]
= {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
Richard Biener changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #11 from CVS Commits ---
The master branch has been updated by Richard Biener :
https://gcc.gnu.org/g:7c76c876e917a1f20a788f602cc78fff7d0a2a65
commit r14-4527-g7c76c876e917a1f20a788f602cc78fff7d0a2a65
Author: Richard Biener
Date:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #10 from rguenther at suse dot de ---
On Tue, 10 Oct 2023, juzhe.zhong at rivai dot ai wrote:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
>
> --- Comment #9 from JuzheZhong ---
> (In reply to Richard Biener from comment
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #9 from JuzheZhong ---
(In reply to Richard Biener from comment #8)
> ic = "\x00\x03\x06\t\f\x0f\x12\x15\x18\x1b\x1e!$\'*-";
> ib = "\x00\x03\x06\t\f\x0f\x12\x15\x18\x1b\x1e!$\'*-";
> vect__1.7_10 = MEM [(char *)&ib];
> vect
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
Richard Biener changed:
What|Removed |Added
Assignee|unassigned at gcc dot gnu.org |rguenth at gcc dot
gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #7 from JuzheZhong ---
(In reply to Andrew Pinski from comment #6)
> (In reply to JuzheZhong from comment #5)
> > (In reply to Andrew Pinski from comment #4)
> > > The issue for aarch64 with SVE is that MASK_LOAD is not optimized:
>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #6 from Andrew Pinski ---
(In reply to JuzheZhong from comment #5)
> (In reply to Andrew Pinski from comment #4)
> > The issue for aarch64 with SVE is that MASK_LOAD is not optimized:
> >
> > ic = "\x00\x03\x06\t\f\x0f\x12\x15\x18
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #5 from JuzheZhong ---
(In reply to Andrew Pinski from comment #4)
> The issue for aarch64 with SVE is that MASK_LOAD is not optimized:
>
> ic = "\x00\x03\x06\t\f\x0f\x12\x15\x18\x1b\x1e!$\'*-";
> ib = "\x00\x03\x06\t\f\x0f\x12\
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #4 from Andrew Pinski ---
The issue for aarch64 with SVE is that MASK_LOAD is not optimized:
ic = "\x00\x03\x06\t\f\x0f\x12\x15\x18\x1b\x1e!$\'*-";
ib = "\x00\x03\x06\t\f\x0f\x12\x15\x18\x1b\x1e!$\'*-";
vect__1.7_9 = .MASK_LOA
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #3 from Andrew Pinski ---
If you add `-fno-vect-cost-model` to aarch64 compiling, then it uses SVE and
does not optimize to just `return 0`.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
Andrew Pinski changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111751
--- Comment #1 from Andrew Pinski ---
AARCH64 did vectorize the code just using non-SVE which then allowed to be
optimized too.
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