https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
JuzheZhong changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #19 from Richard Biener ---
(In reply to JuzheZhong from comment #18)
> (In reply to JuzheZhong from comment #17)
> > Confirm by this try:
> > https://godbolt.org/z/q7zx5zG5e
> >
> > Both ARM SVE trunk GCC and RISC-V GCC failed to v
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #18 from JuzheZhong ---
(In reply to JuzheZhong from comment #17)
> Confirm by this try:
> https://godbolt.org/z/q7zx5zG5e
>
> Both ARM SVE trunk GCC and RISC-V GCC failed to vectorize simple
> unsigned short shift right, with follo
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #17 from JuzheZhong ---
Confirm by this try:
https://godbolt.org/z/q7zx5zG5e
Both ARM SVE trunk GCC and RISC-V GCC failed to vectorize simple
unsigned short shift right, with following failed information:
:14:1: missed: couldn't ve
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #16 from JuzheZhong ---
(In reply to Richard Biener from comment #15)
> Well, the question is why we arrive here with the two different vector types.
> Can you tell me a relevant cc1 compiler command like for a x86->riscv cross
> tha
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #15 from Richard Biener ---
Well, the question is why we arrive here with the two different vector types.
Can you tell me a relevant cc1 compiler command like for a x86->riscv cross
that exposes the issue?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #14 from JuzheZhong ---
(In reply to rsand...@gcc.gnu.org from comment #12)
> (In reply to JuzheZhong from comment #11)
> > You can see "_9 = _5 >> _8;". We should vectorize SImode instead of HImode.
> > The correct follow should be
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #13 from JuzheZhong ---
I just checked ARM SVE has the same behavior with RISC-V:
https://godbolt.org/z/vY6ecY6Mx
You can see this compiler explorer. ARM trunk GCC SVE failed to vectorize it
too same as RISCV wheras ARM GCC 13.1 ca
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #12 from rsandifo at gcc dot gnu.org
---
(In reply to JuzheZhong from comment #11)
> You can see "_9 = _5 >> _8;". We should vectorize SImode instead of HImode.
> The correct follow should be first extend HI -> SImode, Then vectoriz
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #11 from JuzheZhong ---
I debug vectorizable_shift:
Breakpoint 1, vectorizable_shift (vinfo=0x3fb45d0, stmt_info=0x3fb5ea0,
gsi=0x0, vec_stmt=0x0, slp_node=0x0, cost_vec=0x7fffc648) at
../../../riscv-gcc/gcc/tree-vect-stmts.cc:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #10 from rsandifo at gcc dot gnu.org
---
(In reply to JuzheZhong from comment #9)
> I seems that we must support widen shift pattern in RISCV port even though
> we don't have widen shift instructions ?
I doubt it. Seems like one o
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #9 from JuzheZhong ---
The name is correct, since the same pattern works for uint32 but fail to work
for uint16
I checked the build file:
CODE_FOR_vlshrrvvm1hi3 = 10350,
>> Well, that means we do not have a vector mode for HImode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #8 from Richard Biener ---
(In reply to JuzheZhong from comment #6)
> (In reply to Richard Biener from comment #3)
> > it looks like you don't support vector short logical shift? For some reason
> > vect_recog_over_widening_pattern
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #7 from Richard Biener ---
(In reply to JuzheZhong from comment #5)
> (In reply to Richard Biener from comment #3)
> > it looks like you don't support vector short logical shift? For some reason
> > vect_recog_over_widening_pattern
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #6 from JuzheZhong ---
(In reply to Richard Biener from comment #3)
> it looks like you don't support vector short logical shift? For some reason
> vect_recog_over_widening_pattern doesn't check whether the demoted operation
> is su
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #5 from JuzheZhong ---
(In reply to Richard Biener from comment #3)
> it looks like you don't support vector short logical shift? For some reason
> vect_recog_over_widening_pattern doesn't check whether the demoted operation
> is su
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
--- Comment #4 from JuzheZhong ---
(In reply to Richard Biener from comment #3)
> it looks like you don't support vector short logical shift? For some reason
> vect_recog_over_widening_pattern doesn't check whether the demoted operation
> is su
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110897
Richard Biener changed:
What|Removed |Added
Last reconfirmed||2023-08-04
Target|riscv
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