[Bug target/98934] Very poor code generation for SSE 8-bit vector right shift

2021-08-25 Thread crazylht at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98934 --- Comment #4 from Hongtao.liu --- (In reply to Andrew Pinski from comment #2) > This is really poor with -mavx512f even. We should be able to do it like (define_expand "vashr3" [(set (match_operand:VI12_128 0 "register_operand") (ashi

[Bug target/98934] Very poor code generation for SSE 8-bit vector right shift

2021-08-24 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98934 --- Comment #3 from Andrew Pinski --- *** Bug 98399 has been marked as a duplicate of this bug. ***

[Bug target/98934] Very poor code generation for SSE 8-bit vector right shift

2021-08-24 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98934 --- Comment #2 from Andrew Pinski --- This is really poor with -mavx512f even. We should be able to do it like (which is what LLVM does): vpmovzxbd %xmm1, %zmm1 vpmovzxbd %xmm0, %zmm0 vpsravd %zmm1, %zmm0, %zmm

[Bug target/98934] Very poor code generation for SSE 8-bit vector right shift

2021-02-02 Thread rguenth at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98934 Richard Biener changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED