[Bug target/82445] ARM target generates unaligned STRD instruction

2017-10-19 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 Richard Earnshaw changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/82445] ARM target generates unaligned STRD instruction

2017-10-19 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 --- Comment #7 from Richard Earnshaw --- Author: rearnsha Date: Thu Oct 19 13:14:55 2017 New Revision: 253891 URL: https://gcc.gnu.org/viewcvs?rev=253891&root=gcc&view=rev Log: [ARM] PR 82445 - suppress 32-bit aligned ldrd/strd peepholing with -

[Bug target/82445] ARM target generates unaligned STRD instruction

2017-10-19 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 --- Comment #8 from Richard Earnshaw --- Author: rearnsha Date: Thu Oct 19 13:16:42 2017 New Revision: 253892 URL: https://gcc.gnu.org/viewcvs?rev=253892&root=gcc&view=rev Log: [ARM] PR 82445 - suppress 32-bit aligned ldrd/strd peepholing with -

[Bug target/82445] ARM target generates unaligned STRD instruction

2017-10-19 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 --- Comment #6 from Richard Earnshaw --- Author: rearnsha Date: Thu Oct 19 13:10:42 2017 New Revision: 253890 URL: https://gcc.gnu.org/viewcvs?rev=253890&root=gcc&view=rev Log: [ARM] PR 82445 - suppress 32-bit aligned ldrd/strd peepholing with -

[Bug target/82445] ARM target generates unaligned STRD instruction

2017-10-18 Thread petrcvekcz at gmail dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 Petr Cvek changed: What|Removed |Added CC||petrcvekcz at gmail dot com --- Comment #5 f

[Bug target/82445] ARM target generates unaligned STRD instruction

2017-10-09 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 Richard Earnshaw changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigne

[Bug target/82445] ARM target generates unaligned STRD instruction

2017-10-09 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 --- Comment #4 from Richard Earnshaw --- looks like gen_operands_ldrd_strd should be checking for this and failing if the alignment is not suitable for the target architecture.

[Bug target/82445] ARM target generates unaligned STRD instruction

2017-10-06 Thread rguenth at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 Richard Biener changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/82445] ARM target generates unaligned STRD instruction

2017-10-06 Thread agraf at suse dot de
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 --- Comment #2 from Alexander Graf --- (In reply to Richard Biener from comment #1) > Does -fno-store-merging fix it? Yes, but it generates worse code than -march=armv5 (which does not support STRD) does: -march=armv6 -fno-store-merging: >

[Bug target/82445] ARM target generates unaligned STRD instruction

2017-10-06 Thread rguenth at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 Richard Biener changed: What|Removed |Added Keywords||wrong-code Target|ARM