[Bug target/115817] [AVR] Suboptimal code for zeroing SRAM byte from ISR

2025-03-07 Thread gjl at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115817 Georg-Johann Lay changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/115817] [AVR] Suboptimal code for zeroing SRAM byte from ISR

2025-02-16 Thread gjl at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115817 --- Comment #9 from Georg-Johann Lay --- What can be used as a kind of work-around (and may be even better than the code with improved Binutils as proposed above), is to hide the value of 0 from the compiler: volatile uint8_t var; __attribute(

[Bug target/115817] [AVR] Suboptimal code for zeroing SRAM byte from ISR

2025-02-16 Thread gjl at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115817 --- Comment #8 from Georg-Johann Lay --- See https://sourceware.org/bugzilla/show_bug.cgi?id=32704

[Bug target/115817] [AVR] Suboptimal code for zeroing SRAM byte from ISR

2025-02-16 Thread gjl at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115817 Georg-Johann Lay changed: What|Removed |Added CC||ul...@t-online.de --- Comment #7 fro

[Bug target/115817] [AVR] Suboptimal code for zeroing SRAM byte from ISR

2025-01-19 Thread dimich.dmb at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115817 --- Comment #6 from Dmytro Bagrii --- (In reply to Georg-Johann Lay from comment #5) Thank you for explanation. > LDI cannot be used since it only allows R16...R31. I meant do not treat 0 as a special value and use LDI R24,0x00 The same as fo

[Bug target/115817] [AVR] Suboptimal code for zeroing SRAM byte from ISR

2025-01-19 Thread gjl at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115817 --- Comment #5 from Georg-Johann Lay --- (In reply to Dmytro Bagrii from comment #4) > gcc is smart enough not to initialize R1 when it is not used. Actually not. The decision whether __zero_reg__ is required in an ISR is worked out by the asse

[Bug target/115817] [AVR] Suboptimal code for zeroing SRAM byte from ISR

2024-07-08 Thread dimich.dmb at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115817 --- Comment #4 from Dmytro Bagrii --- Of course, there are various cores, i'm just speculating regarding necessity of preserving R1. For now the issue is worked around with inline assembler. It was surprise for me to see the .text size increase

[Bug target/115817] [AVR] Suboptimal code for zeroing SRAM byte from ISR

2024-07-08 Thread gjl at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115817 --- Comment #3 from Georg-Johann Lay --- Setting R1 to 0 in an ISR prologue is not redundant, because R1 may be non-zero due to a variety of reasons, for example when the interrupted code uses MUL just to mention one. Moreover, on Reduced Tiny

[Bug target/115817] [AVR] Suboptimal code for zeroing SRAM byte from ISR

2024-07-08 Thread dimich.dmb at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115817 --- Comment #2 from Dmytro Bagrii --- Yes, in "regular" function single STS for storing zero is better than LDI/STS for storing non-zero, assuming r1 is already zeroed. If it were guaranteed that ISR cannot be invoked before libc's .init2 secti

[Bug target/115817] [AVR] Suboptimal code for zeroing SRAM byte from ISR

2024-07-08 Thread gjl at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115817 Georg-Johann Lay changed: What|Removed |Added Priority|P3 |P4 Keywords|