[Bug target/113282] RISC-V non-atomic union store/load reordering

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113282 Andrew Pinski changed: What|Removed |Added Resolution|FIXED |INVALID --- Comment #5 from Andrew Pins

[Bug target/113282] RISC-V non-atomic union store/load reordering

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113282 Patrick O'Neill changed: What|Removed |Added Resolution|INVALID |FIXED --- Comment #4 from Patrick O'N

[Bug target/113282] RISC-V non-atomic union store/load reordering

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113282 --- Comment #3 from Andrew Pinski --- Note -fno-strict-aliasing will allow the code to work the way you want it to work.

[Bug target/113282] RISC-V non-atomic union store/load reordering

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113282 --- Comment #2 from Andrew Pinski --- > On x86 this problem Yes x86 does not enable the scheduler before ra and has less registers so the scheduler is not as aggressive as on the other targets. Note this is standard strict aliasing issue even.

[Bug target/113282] RISC-V non-atomic union store/load reordering

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113282 Andrew Pinski changed: What|Removed |Added Resolution|--- |INVALID Keywords|