[Bug target/113023] RISCV redundant code for loading fixed address

2023-12-14 Thread schwab--- via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113023 --- Comment #5 from Andreas Schwab --- If the linker relaxation does not remove a relaxable move then it is a bug in the linker.

[Bug target/113023] RISCV redundant code for loading fixed address

2023-12-14 Thread iwfinlay at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113023 --- Comment #4 from Iain Finlay --- GCC does know that it needs LANCHOR0 and LANCHOR0+4 (meaning a difference of 4). The 12-bit lower portion can be provided in the load and store commands. It seems just an implementation choice in pcnt0 that it

[Bug target/113023] RISCV redundant code for loading fixed address

2023-12-14 Thread iwfinlay at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113023 --- Comment #3 from Iain Finlay --- It does not get removed. It ends up in the final image. It is also redundant because load and store can also add a 12 bit signed offset.

[Bug target/113023] RISCV redundant code for loading fixed address

2023-12-14 Thread schwab--- via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113023 --- Comment #2 from Andreas Schwab --- The insn is _not_ redundant, there is a relocation on it. The linker relaxation will eventually remove it when it becomes unnessessary.

[Bug target/113023] RISCV redundant code for loading fixed address

2023-12-14 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113023 Andrew Pinski changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRMED