[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2024-01-08 Thread vineetg at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #9 from Vineet Gupta --- (In reply to JuzheZhong from comment #5) > Support VLS codegen with -mrvv-vector-bits and attribute is reasonable to be > landed on GCC-14. > > Could you first implement -mrvv-vector-bits feature ? > > I ha

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2023-12-05 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #8 fro

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2023-12-01 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #7 from JuzheZhong --- (In reply to Vineet Gupta from comment #6) > (In reply to JuzheZhong from comment #5) > > > Support VLS codegen with -mrvv-vector-bits and attribute is reasonable to be > > landed on GCC-14. > > I don't think

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2023-12-01 Thread vineetg at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #6 from Vineet Gupta --- (In reply to JuzheZhong from comment #5) > Support VLS codegen with -mrvv-vector-bits and attribute is reasonable to be > landed on GCC-14. I don't think that is the reqmt for this issue. Just defining the

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2023-12-01 Thread juzhe.zhong at rivai dot ai via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #5 from JuzheZhong --- Support VLS codegen with -mrvv-vector-bits and attribute is reasonable to be landed on GCC-14. But currently we are busy with fixing bugs (me, Robin, Lixu@eswin, Li Pan@intel). You can see gcc-patch list...

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2023-12-01 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #4 from Andrew Pinski --- (In reply to Vineet Gupta from comment #3) > I agree, but what xsimd does is not under our control. Whoever wants to use > xsimd for whatever reasons, we can allow gcc to be used similarly to llvm > and cert

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2023-12-01 Thread vineetg at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 Vineet Gupta changed: What|Removed |Added CC||vineetg at gcc dot gnu.org --- Comment #

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2023-12-01 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #2 from Andrew Pinski --- Note the reality is xsimd was not thought out for SIMD but rather just fixed length extensions. It seems more like a major shift that needs to happen to these libraries and stop just thinking fixed length re

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2023-12-01 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 --- Comment #1 from Andrew Pinski --- >gcc doesn't, which is a bit of pain for downstream projects such as xsimd. Does it even make sense to define this? Projects like xsimd seems to be good for fixed length SIMD but it seems to have a broken i

[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

2023-12-01 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817 Andrew Pinski changed: What|Removed |Added Severity|normal |enhancement