https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103503
--- Comment #7 from H. Peter Anvin ---
Note: this is now implemented for x86, but it affects other targets as well.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103503
--- Comment #6 from GCC Commits ---
The master branch has been updated by H.J. Lu :
https://gcc.gnu.org/g:a96549dce7636edfc693bf758ef27fcd8adc6161
commit r14-8469-ga96549dce7636edfc693bf758ef27fcd8adc6161
Author: H.J. Lu
Date: Tue Jan 23 06
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103503
H.J. Lu changed:
What|Removed |Added
Ever confirmed|0 |1
Status|UNCONFIRMED
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103503
--- Comment #4 from H. Peter Anvin ---
The interrupt attribute typically does two things:
1. It changes the return instruction;
2. It marks all registers as saved.
2 is exactly the *opposite* of what I want; I would like to improve performance
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103503
Andrew Pinski changed:
What|Removed |Added
Severity|normal |enhancement
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103503
--- Comment #3 from Andrew Pinski ---
the only major target which does not have the interrupt attribute is aarch64.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103503
--- Comment #2 from Andrew Pinski ---
RISCV does have the interrupt attribute too which should work here.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103503
--- Comment #1 from Andrew Pinski ---
x86 (and I think MIPS) has an interrupt attribute, will that work instead?
