https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102211
--- Comment #2 from Hongtao.liu ---
According to *movsi_internal and *movdi_64bit, SImode, and DImode can be placed
into FP_REGS, but in riscv_hard_regno_mode_ok, SImode/DImode is not allowed to
be allocated as FP_REGS, the mismatch here caues t
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102211
--- Comment #1 from Hongtao.liu ---
But it's ok for
float
foo (float a, long b)
{
union{float a[2];
long b;}c;
c.b = b;
return c.a[0];
}
foo:
fmv.w.x fa0,a0
ret
Which means movement between gpr and float reg is allo
