https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114923
--- Comment #9 from nfxjfg at googlemail dot com ---
Oh, I completely missed that your statement was restricted to "in HW". Normally
there are mechanisms in place that make all CPU-level memory accesses to
registers strictly ordered. (In our hard
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114923
--- Comment #8 from Andrew Pinski ---
(In reply to nfxjfg from comment #7)
> > Note also the order of the writes to reg1 and reg2 might happen in a
> > different order in HW so you need to have a full (HW) write barrier between
> > them to mak
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114923
--- Comment #7 from nfxjfg at googlemail dot com ---
> Note also the order of the writes to reg1 and reg2 might happen in a
> different order in HW so you need to have a full (HW) write barrier between
> them to make sure the write is done in t
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114923
--- Comment #6 from Andrew Pinski ---
Some resources about memory barriers and why they are needed here (for both HW
and SW):
https://en.wikipedia.org/wiki/Memory_barrier
https://www.kernel.org/doc/Documentation/memory-barriers.txt
https://www.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114923
Andrew Pinski changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Resolution|---
