[Bug target/117669] RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error

2024-11-19 Thread wangfeng at eswincomputing dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117669 Feng Wang changed: What|Removed |Added CC||wangfeng at eswincomputing dot com --- Com

[Bug rtl-optimization/109592] Failure to recognize shifts as sign/zero extension

2023-05-29 Thread wangfeng at eswincomputing dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 --- Comment #8 from Feng Wang --- (In reply to Jeffrey A. Law from comment #7) > Attached is what I cobbled together. It doesn't use magic numbers. But it > doesn't yet handle zero extensions in the simplify-rtx code. But I think it > shows t

[Bug rtl-optimization/109592] Failure to recognize shifts as sign/zero extension

2023-05-11 Thread wangfeng at eswincomputing dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 --- Comment #5 from Feng Wang --- I found something interesting, these operations such as zero_extend,sign_extend,zero_extract,sign_extract will be considered as compound operation and will transform to the approriate shifts and AND operations(T

[Bug rtl-optimization/109592] Failure to recognize shifts as sign/zero extension

2023-04-23 Thread wangfeng at eswincomputing dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 --- Comment #2 from Feng Wang --- (In reply to Feng Wang from comment #1) > Hi Jeff, > > I have modified some code according to your suggestion. > In simplify-rtx.cc I add below part in canonicalize_shift: > if ((code == ASHIFTRT) >

[Bug rtl-optimization/109592] Failure to recognize shifts as sign/zero extension

2023-04-23 Thread wangfeng at eswincomputing dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 Feng Wang changed: What|Removed |Added CC||wangfeng at eswincomputing dot com --- Com