Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: nekotekina at gmail dot com
Target Milestone: ---
Hello, noticed that gcc generates redundant sequence of instructions for code
that does 128-bit byteswap implemented with 2 64-bit byteswap intrinsics. I
narrowed it
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103973
--- Comment #4 from Ivan ---
So there is nothing to improve here? That's good to know, I suppose it can be
closed then.
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: nekotekina at gmail dot com
Target Milestone: ---
Hello, I may be missing something here but the generated code seems strange and
suboptimal. It looks like all 4
: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: nekotekina at gmail dot com
Target Milestone: ---
Hello, this problem is seemingly not specific to GCC and is probably well
known. Loading or storing 16-byte (or larger
Severity: normal
Priority: P3
Component: c++
Assignee: unassigned at gcc dot gnu.org
Reporter: nekotekina at gmail dot com
Target Milestone: ---
GCC generates seemingly unoptimized sequence of instructions in certain cases
(can't tell exactly what tri
Priority: P3
Component: tree-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: nekotekina at gmail dot com
Target Milestone: ---
Hello, I was trying to use VPMOVSXWD and other PMOVSX* intrinsics and also
emulate them for SSE2 targets. I noticed two
NCONFIRMED
Severity: normal
Priority: P3
Component: c++
Assignee: unassigned at gcc dot gnu.org
Reporter: nekotekina at gmail dot com
Target Milestone: ---
I was not using gcc compiler directly (it happened for Travis build), sorry if
the information is mis
