[Bug target/117831] [RISCV] A dead loop occurs when calculating the multiplication of two uint64 integers under rv32 -Os

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117831 --- Comment #2 from liu xu --- (In reply to Xi Ruoyao from comment #1) > Where is the dead loop? What values of a and b triggers it? No matter what input values I use, after performing several calculations, it will fall into the following loop

[Bug c/117831] New: [RISCV] A dead loop occurs when calculating the multiplication of two uint64 integers under rv32 -Os

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117831 Bug ID: 117831 Summary: [RISCV] A dead loop occurs when calculating the multiplication of two uint64 integers under rv32 -Os Product: gcc Version: 15.0 Status: UNCONFIRM

[Bug c/113715] New: RISC-V: If the Zcmp is enabled, the a0 register operates abnormally when the program returns

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113715 Bug ID: 113715 Summary: RISC-V: If the Zcmp is enabled, the a0 register operates abnormally when the program returns Product: gcc Version: 14.0 Status: UNCONFIRMED

[Bug c/112559] New: The -fno-builtin option affects the instruction generation of the program

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112559 Bug ID: 112559 Summary: The -fno-builtin option affects the instruction generation of the program Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: norm

[Bug target/112538] New: [RISC-V] Failed to disable V-ext autovectorization using the '--param riscv-autovec-preference=none'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112538 Bug ID: 112538 Summary: [RISC-V] Failed to disable V-ext autovectorization using the '--param riscv-autovec-preference=none' Product: gcc Version: 14.0 Status: UNCONFIRM

[Bug middle-end/111621] [RISC-V] Bad register allocation in vadd.vi may cause operational error

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111621 --- Comment #2 from liu xu --- I'm sorry about that and will notice that next time. The toolchain I used was built using the gcc master branch, and another point that needs to be added is that only the vadd.vi instruction with mask will encount

[Bug middle-end/111621] New: [RISC-V] Bad register allocation in vadd.vi may cause operational error

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111621 Bug ID: 111621 Summary: [RISC-V] Bad register allocation in vadd.vi may cause operational error Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/110448] New: [RISC-V] RVV intrinsic api test error

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110448 Bug ID: 110448 Summary: [RISC-V] RVV intrinsic api test error Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target