[Bug target/43862] GCC doesn't use 16-bit armv5te multiplies when possible

--- Comment #1 from lessen42+gcc at gmail dot com 2010-04-23 03:03 --- Created an attachment (id=20467) --> (http://gcc.gnu.org/bugzilla/attachment.cgi?id=20467&action=view) smul/smla in C -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43862

[Bug target/43862] New: GCC doesn't use 16-bit armv5te multiplies when possible

when possible Product: gcc Version: 4.5.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target AssignedTo: unassigned at gcc dot gnu dot org ReportedBy: lessen42+gcc at gmail dot com GCC build triplet: x

[Bug inline-asm/43860] New: Inline asm doesn't respect q clobbers

Severity: normal Priority: P3 Component: inline-asm AssignedTo: unassigned at gcc dot gnu dot org ReportedBy: lessen42+gcc at gmail dot com GCC build triplet: x86_64-apple-darwin GCC host triplet: x86_64-apple-darwin GCC target triplet: arm-none-linux-gnueabi http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43860

[Bug middle-end/16660] attribute((aligned)) doesn't work for variables on the stack for greater than required alignement

--- Comment #18 from lessen42+gcc at gmail dot com 2009-08-20 08:49 --- This still doesn't work on ARM either (tested with 4.4.0). The EABI only mandates the stack be 8 byte aligned, and gcc silently clips any alignment request above 8 bytes to 8 (so even if the stack were 16

[Bug middle-end/40893] ARM and PPC truncate intermediate operations unnecessarily

--- Comment #1 from lessen42+gcc at gmail dot com 2009-07-28 22:27 --- More specifically, on x86_64 the following is generated with gcc-4.4 -O3 -march=core2 -S _dct2x2dc_dconly: movswl 2(%rdi),%edx pushq %rbp addw(%rdi), %dx movswl 6(%rdi),%eax

[Bug middle-end/40893] New: ARM and PPC truncate intermediate operations unnecessarily

ecessarily Product: gcc Version: 4.4.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle-end AssignedTo: unassigned at gcc dot gnu dot org ReportedBy: lessen42+gcc at gmail dot com GCC host triplet:

[Bug middle-end/40887] GCC generates suboptimal code for indirect function calls on ARM

--- Comment #3 from lessen42+gcc at gmail dot com 2009-07-28 08:45 --- (In reply to comment #2) > The point made is correct but there is something you've missed in your patch ! > loading lr with the address of the function you want to call, destroys the > return address ,