[Bug target/116466] The standard instruction pattern of RISC-V addv has generated an unnecessary instruction.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116466 --- Comment #4 from cui xu --- (In reply to Jeffrey A. Law from comment #2) > Looking at this, I would fully expect that in an optimizing compilation that > the redundant extension would be eliminated. Are you seeing the redundant > sign exten

[Bug target/116466] The standard instruction pattern of RISC-V addv has generated an unnecessary instruction.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116466 --- Comment #3 from cui xu --- (In reply to Jeffrey A. Law from comment #2) > Looking at this, I would fully expect that in an optimizing compilation that > the redundant extension would be eliminated. Are you seeing the redundant > sign exten

[Bug target/116466] New: The standard instruction pattern of RISC-V addv has generated an unnecessary instruction.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116466 Bug ID: 116466 Summary: The standard instruction pattern of RISC-V addv has generated an unnecessary instruction. Product: gcc Version: 14.2.1 Status: UNCONFIRMED