https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110592
--- Comment #8 from Koakuma ---
Created attachment 55529
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55529&action=edit
Proposed patch for relaxing the guards of barrier emission
Hello, sorry that I only got to reply now.
And yeah, I fi
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110592
Bug ID: 110592
Summary: [SPARC] GCC should default to TSO memory model when
compiling for sparc32
Product: gcc
Version: 12.2.1
Status: UNCONFIRMED
Severity: no
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105782
--- Comment #4 from Koakuma ---
(In reply to Eric Botcazou from comment #3)
> I guess that, under high register pressure, the register allocator rather
> uses floating-point registers than spllling values on the stack.
I suppose so?
However, I
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105782
--- Comment #2 from Koakuma ---
Created attachment 53066
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53066&action=edit
Vectorization log from -fopt-info-vec-all
(In reply to Richard Biener from comment #1)
> You can check -fopt-info-ve
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105782
Bug ID: 105782
Summary: [sparc64] Emission of questionable movxtod/movdtox
with -mvis3
Product: gcc
Version: 12.1.0
Status: UNCONFIRMED
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105292
Bug ID: 105292
Summary: [sparc64] ICE in expand_expr_real_2 on sparc64 when
compiling with -mcpu=niagara4
Product: gcc
Version: 11.2.0
Status: UNCONFIRMED
Seve
