[Bug target/105339] New: [x86] missing AVX-512F scalef functions when optimization is disabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105339 Bug ID: 105339 Summary: [x86] missing AVX-512F scalef functions when optimization is disabled Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal

[Bug target/101714] New: [POWER] vec_min / vec_max handles NaN incorrectly when evaluated at compile time

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101714 Bug ID: 101714 Summary: [POWER] vec_min / vec_max handles NaN incorrectly when evaluated at compile time Product: gcc Version: 10.2.1 Status: UNCONFIRMED Sever

[Bug target/101614] [s390] vec_signed requires z15, docs say z13

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101614 Evan Nemerson changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/101614] New: [s390] vec_signed requires z15, docs say z13

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101614 Bug ID: 101614 Summary: [s390] vec_signed requires z15, docs say z13 Product: gcc Version: 11.1.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: t

[Bug target/100927] New: [sse2] floating point to integer conversion functions incorrect results w/ NaN constants + optimization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100927 Bug ID: 100927 Summary: [sse2] floating point to integer conversion functions incorrect results w/ NaN constants + optimization Product: gcc Version: 11.1.1 Status: UNCO

[Bug target/100762] [mips+msa] ICE when comparing 64 bit vectors

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100762 --- Comment #1 from Evan Nemerson --- It's not just comparisons. <<, >>, /, * also don't work. AFAICT only bitwise operations and +/- work, as well as everything with a 64-bit element type (i.e., a vector of one element)… 8/16/32-bit elements

[Bug target/100762] New: [mips+msa] ICE when comparing 64 bit vectors

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100762 Bug ID: 100762 Summary: [mips+msa] ICE when comparing 64 bit vectors Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: t

[Bug target/100761] New: [mips+msa] ICE when using __builtin_convertvector to convert from u8x8 to u8x16

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100761 Bug ID: 100761 Summary: [mips+msa] ICE when using __builtin_convertvector to convert from u8x8 to u8x16 Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severi

[Bug target/97248] [mips] unrecognizable insn when left shifting uint64 vector by scalar with MSA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97248 --- Comment #1 from Evan Nemerson --- SImilar issue with right shift: typedef long a; typedef struct { a b __attribute__((__vector_size__(64))); } c; void d() { int e; c f, g; f.b = g.b >> e; } $ mips64el-linux-gnuabi64-g++-10 -march=

[Bug target/100760] New: [mips + msa] ICE: maximum number of generated reload insns per insn achieved

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100760 Bug ID: 100760 Summary: [mips + msa] ICE: maximum number of generated reload insns per insn achieved Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity:

[Bug target/95782] [ppc64le] ICE in _cpp_pop_context

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95782 --- Comment #1 from Evan Nemerson --- This seems to also happen on s390x with -mzvector: # s390x-linux-gnu-gcc-10 -march=z14 -mzvector -o test test.c test.c:4:1: internal compiler error: in _cpp_pop_context, at libcpp/macro.c:2644 4 | b(vec

[Bug target/99754] New: [sse2] new _mm_loadu_si16 and _mm_loadu_si32 implemented incorrectly

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99754 Bug ID: 99754 Summary: [sse2] new _mm_loadu_si16 and _mm_loadu_si32 implemented incorrectly Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug target/99698] [aarch64] Impossible to accurately detect extensions using preprocessor

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99698 --- Comment #2 from Evan Nemerson --- Nice, thanks! That would at least make testing possible, though I still think that just checking __ARM_FEATURE_SHA3 should be sufficient, and ktkachov's comment reinforces that.

[Bug target/99698] New: [aarch64] Impossible to accurately detect extensions using preprocessor

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99698 Bug ID: 99698 Summary: [aarch64] Impossible to accurately detect extensions using preprocessor Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: normal

[Bug target/98734] New: ABI diagnostics emitted despite always_inline attribute

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98734 Bug ID: 98734 Summary: ABI diagnostics emitted despite always_inline attribute Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal Prio

[Bug target/98521] [x86] Missing/incorrect XOP functions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98521 --- Comment #1 from Evan Nemerson --- Sorry, VS has two parametrs for _mm_frcz_ss and _mm_frcz_sd; clang is the outlier. So just the missing _mm256_cmov_si256.

[Bug target/98521] New: [x86] Missing/incorrect XOP functions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98521 Bug ID: 98521 Summary: [x86] Missing/incorrect XOP functions Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/98428] New: [11 regression] ICE with omp simd loop + optimization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98428 Bug ID: 98428 Summary: [11 regression] ICE with omp simd loop + optimization Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compone

[Bug target/97248] New: [mips] unrecognizable insn when left shifting uint64 vector by scalar with MSA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97248 Bug ID: 97248 Summary: [mips] unrecognizable insn when left shifting uint64 vector by scalar with MSA Product: gcc Version: unknown Status: UNCONFIRMED Severity