[Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.

2005-01-04 Thread andersca at gnome dot org
--- Additional Comments From andersca at gnome dot org 2005-01-04 18:09 --- Confirming that this does fix the error for me. Thanks a lot! -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19235

[Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.

2005-01-03 Thread andersca at gnome dot org
--- Additional Comments From andersca at gnome dot org 2005-01-03 19:46 --- Looking at the Intel reference documentation available from ftp://download.intel.com/design/ Pentium4/manuals/25366614.pdf MOVQ has the following opcodes: 0F 6F /r MOVQ mm, mm/m64 Move quadword from mm/m64 to

[Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.

2005-01-03 Thread andersca at gnome dot org
--- Additional Comments From andersca at gnome dot org 2005-01-03 15:21 --- The patch does not fix the problem; the xmm registers are used anyway... -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19235

[Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.

2005-01-03 Thread andersca at gnome dot org
--- Additional Comments From andersca at gnome dot org 2005-01-03 12:52 --- I'm going a make bootstrap on this right now; I'll report the test results as soon as it finishes. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19235