https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114675
Bug ID: 114675
Summary: warning for "reference to not fully constructed
object"
Product: gcc
Version: 13.1.1
Status: UNCONFIRMED
Severity: normal
Pri
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113981
Bug ID: 113981
Summary: risc-v: non-void C++ function with no return statement
has no ret
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113980
Bug ID: 113980
Summary: risc-v: unnecessary sign-extend after lw, and more
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Componen
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111704
Bug ID: 111704
Summary: ICE in extract_insn, at recog.cc:2791 on
aarch64-linux-gnu during RTL pass: cprop_hardreg
Product: gcc
Version: 12.3.0
Status: UNCONFIRMED
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109930
--- Comment #5 from Simon Richter ---
> Btw if you know the old state then there is presumably no concurrent access
> here and so you don't need atomic, let alone sequential consistency.
I know it in some, but not all cases.
Basically, what I
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109930
--- Comment #3 from Simon Richter ---
I was looking at ARMv7 initially.
If I understood the implementation correctly, this can be a generic
optimization.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109930
Bug ID: 109930
Summary: transform atomic exchange to unconditional store when
old value is unused?
Product: gcc
Version: 13.1.1
Status: UNCONFIRMED
Severity: n