[Bug middle-end/116860] [15 Regression] New test case gcc.dg/tree-ssa/fold-xor-and-or.c from r15-3866-ga88d6c6d777ad7 fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116860 --- Comment #6 from Jovan Vukic --- Now I see that I wasn't specific enough, sorry. These tests are passing now for RISC-V, since there has been a regression there too, due to LOGICAL_OP_NON_SHORT_CIRCUIT being defined as 0.

[Bug target/113035] RISC-V: regression testsuite errors -mtune=sifive-7-series

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113035 Jovan Vukic changed: What|Removed |Added CC||jovan.vu...@rt-rk.com --- Comment #5 from

[Bug middle-end/116860] [15 Regression] New test case gcc.dg/tree-ssa/fold-xor-and-or.c from r15-3866-ga88d6c6d777ad7 fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116860 Jovan Vukic changed: What|Removed |Added CC||jovan.vu...@rt-rk.com --- Comment #5 from

[Bug target/117011] New: RISC-V: Logic overlap in IF_THEN_ELSE case for instruction cost calculation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117011 Bug ID: 117011 Summary: RISC-V: Logic overlap in IF_THEN_ELSE case for instruction cost calculation Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: no

[Bug target/115921] Missed optimization: and->ashift might be cheaper than ashift->and on typical RISC targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115921 Jovan Vukic changed: What|Removed |Added CC||jovan.vu...@rt-rk.com --- Comment #2 from