My port have insns like
add symbol_ref, r1
We emit relocation entries for symbol_ref.
Now CSE (-O2) combines insns like below
mov symbol_ref, r0
add const_int, r0
add r0, r1
to
add symbol_ref + const_int, r1
The relocation entry generated for this insn look like
symbol + addend.
The result
--- Nathan Sidwell <[EMAIL PROTECTED]> wrote:
> Sanjiv Kumar Gupta wrote:
>
> > add symbol_ref + const_int, r1
> >
> > The relocation entry generated for this insn look
> like
> > symbol + addend.
> >
> > The resultant value is beoyond the
--- Nathan Sidwell <[EMAIL PROTECTED]> wrote:
> Sanjiv Kumar Gupta wrote:
>
> >
> > Thanks for a prompt reply, Nathan.
> > The add insn can take a symbol_ref, which is
> converted
> > to const_int during relocation. But I don't want
> t
Nathan Sidwell wrote:
Sanjiv Kumar Gupta wrote:
calculated by linker. Now
add r1, foo
add r1, 10
add r1, -10
are okay but add r1, foo + 10
add r1, -10 are not, since (foo + 10) may overflow during
relocation, so the value (foo + 10) && 0xff inserted
by linker is not correct.
> Sanjiv Kumar Gupta wrote:
>
> > > What is stopping the value of 'foo' itself being
> > 255?
> > Programmer will get an overflow error for that
> during linking.
>
> For my curiosity, what's the background here? Do you
> really only have 2
> add1 r1, segment_base, (a - 40)
> add2 r1, 40
read this as
add2 r1, the value of j
>
> Since 'a' is at the boundary of segment so 'a - 40'
> causes relocation overflow.
>
> But the same code works without -O2, because that
> generates code like
> add1 r1, segment_base,
--- James E Wilson <[EMAIL PROTECTED]> wrote:
> Sanjiv Kumar Gupta wrote:
> > But I don't want to
> > allow expressions like (const:SI (plus:SI
> > symbol_ref:SI) (const_int)) in the insn.
> > How should I do that, do I need to implement
> > LEGITI
I am using gcc 3.3.1 release as my port, and looks
like I have hit a problem with greg.
The source program is the sqrt.c math function
__ieee754_sqrt. ( I am pasting the relevent part
here)
typedef union
{
double value;
struct
{
unsigned int lsw;
unsigned int msw;
} parts;
} ieee_
Ian Lance Taylor wrote:
Sanjiv Kumar Gupta <[EMAIL PROTECTED]> writes:
I am using gcc 3.3.1 release as my port, and looks
like I have hit a problem with greg.
You neglected to mention what target you are using.
Ian, the port is for a 32-bit RISC and not complete yet,
hence sti
. I don't know whether gcc mail server
accepts attachments or not,
Oh. It does.
--- Ian Lance Taylor wrote:
Sanjiv Kumar Gupta <[EMAIL PROTECTED]> writes:
I am using gcc 3.3.1 release as my port, and looks
like I have hit a problem with greg.
You neglected to mention what
--- Ian Lance Taylor wrote:
> Sanjiv Kumar Gupta <[EMAIL PROTECTED]> writes:
>
> > >>I couldn't understand why the insns 620 and 621
> are
> > >>being generated here as DI moves.
> > > I'm not sure specifically why it got a DI move
&
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