Abt RTL expression

(insn 8 6 9 1 (parallel [ (set (reg/f:SI 32) (symbol_ref:SI ("t") )) (clobber (reg:CC 21 cc)) ]) -1 (nil) (nil)) Here is an answer to your first question: 8 6 9 are the serial numbers of the current, previous and next instructions in the instru

Compiling with profiling flags

Hello, Is there an option to change the name of the .gcno file that is generated by using profiling flags like -fprofile-generate and later used by -fprofile-use? I read that "For each source file compiled with `-fprofile-arcs', an accompanying `.gcda' file will be placed in the object file dire

Re: Abt RTL expression

> a) To which register is the value of n copied? if a5 is the register > what is 13 and [28] All of those numbers refer to the same register - 13 is the number of the register; a5 is the name of the register (if it is an hard register); [28] is the number of the old pseudo register. (please look

Re: Register Usage - RTL Expression

[EMAIL PROTECTED] wrote on 30/10/2006 15:25:09: > Hi all, > > I am working with GCC Cross compiler 4.1.1. I just some information > regarding the following: > > 1. How does the life1 pass gets the register usage information from > the gcse pass? AFAICT life1 pass calculates the live registers fr

Re: Abt an RTL expression

[EMAIL PROTECTED] wrote on 31/10/2006 12:01:20: > Hello all, > > Can anyone tell me what the below expression means ? > > > (insn 38 37 40 4 (parallel [ > (asm_operands/v ("") ("") 0 [ //line 2 > (reg:SI 32 [ s5.1 ]) > //line 3 >

Re: Induction variable optimization

[EMAIL PROTECTED] wrote on 06/11/2006 03:34:27: > Respected Sir > > I am a M.E.Computer science student and doing project on induction variable > optimization. > > Therefore i am reading the file tree-ssa-loop-ivopts.c of gcc-4.0.2 to know > about what have implemented in that. > > Is there any

-funsafe-math-optimizations and -fno-rounding-math

Hello, -fno-rounding-math enables the transformation of (-(X - Y)) -> (Y - X) in simplify-rtx.c which seems to be the same transformation that enabled by -funsafe-math-optimizations in fold-const.c. If I understand currently -frounding-math means that the rounding mode is important. In that cas

Re: writing a new pass: association with an option string

[EMAIL PROTECTED] wrote on 04/12/2006 10:48:25: > Dear all, > I wrote a new pass for gcc. Actually the pass is always executed, but > I'd like to execute it only if I specify an option from shell (ex. gcc > --mypass pippo.c). How can I do? Maybe adding a gate to your pass which is controlled by

Re: writing a new pass: association with an option string

> Create a new flag in common.opt and read its value in the gate function > of your pass. I *believe* this is documented somewher in the internals > manual, but I'm not sure. See also - http://gcc.gnu.org/wiki/WritingANewPass

Re: Interface for manipulating the abstract syntax tree

> I try to change the front-end tree structure of a c/c++ program as a > side effect of execution of a pragma. The operations that are involved > is to walk through in a tree (i.e "C" block), insertion of a tree > (i.e. statement, block, declaration) in the abstract syntax tree and > deletion of a

Re: Interface for manipulating the abstract syntax tree

> /* below I pass a the tree of the current_function_decl a global > variable in tree.h */ > this_cfun = DECL_STRUCT_FUNCTION(current_function_decl); > FOR_EACH_BB_FN(bb, this_cfun) /* Crashes here, Also tried with > FOR_EACH_BB */ > for (bsi = bsi_start(bb); !bsi_end_p(bsi); b

Re: Interface for manipulating the abstract syntax tree

> > And the code crashes at the macro FOR_EACH_BB_FN.. This is exatly as > it is implemented in cgraph_create_edges() function.. but I think that > the problem is because I call it at wrong time (too early, or too late > - before or after parsing).. Could it be? Yes. You can start by calling it

Re: SSE (Pentium 3) - Is this correct?

> The C code: > > float *vector_add4f(float va[4], const float vb[4]) > { > va[0] += vb[0]; > va[1] += vb[1]; > va[2] += vb[2]; > va[3] += vb[3]; > return va; > } > Now, uh, isn't that four additions? Do I need to do something gcc-specific > to get it to use the 'add-packed-single' ins

Re: Creating a variable declaration of custom type.

> tree type_id, type_node, var_decl; > > type_id = get_identifier("MyType"); > type_node = make_node(POINTER_TYPE); > TYPE_NAME(type_node) = type_id; > var_decl = build(VAR_DECL, get_identifier("t"), type_node); > > But, when I compile my source with the modified GCC (as above) I get > an error:

Re: Creating a variable declaration of custom type.

[EMAIL PROTECTED] wrote on 16/01/2007 17:45:59: > I succeeded to do it as follows: > > tree type_decl = lookup_name(get_identifier("MyType")); > tree type_ptr = build_pointer_type(TREE_TYPE(type_decl)); > tree var_decl = build(VAR_DECL, get_identifier("t"), type_ptr); > pushdecl(var_decl); > > I

Re: About implementing new intrinsic

[EMAIL PROTECTED] wrote on 14/02/2007 19:34:48: > Hi, > > I try to introduce a new intrinsic in gcc's back-end, for the alpha > machines. In doing that, I referenced to the implementaions of altivec > intrinsics for the PowerPC. In the mean time I noticed that the > gcc-4.0 and gcc-4.1 implements

Re: About implementing new intrinsic

[EMAIL PROTECTED] wrote on 18/02/2007 17:01:31: > Hi, > > > > > I am not sure if this message is still relevant. Anyhow, I think > > following another built-in under zero_arg_builtins ("__builtin_alpha_rpcc" > > in alpha.c for example) could help in finding the missing part in this > > implemen

reassociation pass and built-in functions

Hello, We saw that the reassociation pass does not operate on built-in functions, for example: vp3 = vec_madd (vp1, vp2, vp3); In the RTL level the function is expanded to regular insn: (insn 87 91 88 9 (set (reg/v:V4SF 217 [ vp3 ]) (plus:V4SF (mult:V4SF (reg/v:V4SF 219 [ vp1 ])

Re: About implementing new intrinsic

[EMAIL PROTECTED] wrote on 18/02/2007 17:01:31: > Hi, > > > > > I am not sure if this message is still relevant. Anyhow, I think > > following another built-in under zero_arg_builtins ("__builtin_alpha_rpcc" > > in alpha.c for example) could help in finding the missing part in this > > implemen

Generate -zero RTX expression

Hello, I appreciate it if someone could tell me how I can create a -0 RTX expression (like CONST0_RTX)? Thanks, Revital

REG_ALLOC_ORDER and Altivec registers

Hello, I wonder why this order (non-consecutive, decreasing) of Altivec registers was chosen when specifying the allocation order in REG_ALLOC_ORDER. (taken from rs6000.h) /* AltiVec registers. */\ 77, 78,

Re: Manipulating the tree Structure

[EMAIL PROTECTED] wrote on 12/03/2007 16:56:53: > Hi all, > i have a very little question for you. I have a basic block and by a > statement iterator i can obtain a tree structure in the following > manner: > tree stmt = bsi_stmt (si); > I want to use this tree structure to manipulate t

Error in checking compat.exp

Hello, I get the following error while running make check-gcc RUNTESTFLAGS="compat.exp" with mainline gcc version 4.3.0 20070312 on PPC. Revital === g++ tests === Schedule of variations: unix Running target unix Using /usr/local/share/dejagnu/baseboards/unix.exp as board description file

Re: Error in checking compat.exp

> > I'll find a way to fix that. > > Revital, please try this. I've tested it but know better than to check > things in at the end of the day; I'll post it tomorrow. It fixes the problem. Thanks, Revital

Problem with building libgfortran on PPC

Hello, I get the following error on PPC while bootstrapping mainline. Re-runing make I get: collect2: ld terminated with signal 11 [Segmentation fault] make[8]: *** [libstdc++.la] Error 1 Thanks, Revital ranlib .libs/libgfortran.a creating libgfortran.la (cd .libs && rm -f libgfortran.la &&

Re: Problem with building libgfortran on PPC

> > I've been using binutils 2.17 on various distributions of powerpc64-linux > and have had no problem with it. I used binutils 2.15. I guess this is the problem. Thanks, Revital > > Janis

Bootstrap comparison failure with -O2 -funroll-loops -funsafe-math-optimizations

Hello, I get the following error while bootstraping mainline with -O2 -funroll-loops -funsafe-math-optimizations options on PPC. Thanks, Revital make[3]: Leaving directory `/home/revitale/mainline_zero_mve/build' Comparing stages 2 and 3 warning: ./cc1plus-checksum.o differs warning: ./cc1obj-c

Re: 4.3 bootstrap broken on i386-linux

Hello, I get similar error with recent mainline on PPC. ../../../../gcc/libgcc/../libdecnumber/decLibrary.c:71: error: expected ';' before 'd128' ../../../../gcc/libgcc/../libdecnumber/decLibrary.c:73: error: 'd128' undeclared (first use in this function) ../../../../gcc/libgcc/../libdecnumber/de

Re: Question about SMS scheduling windows

Hello Richard, > I ask because in the final range: > > start = early_start; > end = MIN (end, early_start + ii); > /* Schedule the node close to it's predecessors. */ > step = 1; > > END is an exclusive bound. It seems like we might be double-counting here, > and effectiv

Vectorizing invariant data-ref

Hello, The following snippet is from a f90 program which contains a loop that does not get vectorized. SUBROUTINE foo1(nx,ny,nz,arr2) USE globalvar_mod, ONLY : dyinv, xstart, xstop k=1 do j=1,ny do i=1,nx arr1(i,j,k) = arr2(i,j,k ) *dyinv end do end do END SUBROUTINE foo1 The vector

Re: Vectorizing invariant data-ref

Hello, > The testcase is from 459.GemsFDTD, right? dyinv is a regular > global variable. The issue is the global arrays arr1 and arr2 end > up pointing to anything even though the Fortran aliasing rules say > the do not. Yes, the testcase is from 459.GemsFDTD. > We are working on this issue.

error in hash.cc

Hello, I get the following error while compiling gcc -r150679 on ppc Thanks, Revital

Error in fortran/module.c

Hello, I get the following error while bootstrap on x86_64: Thanks, Revital /home/revitale/test_mainline_45/build/./prev-gcc/xgcc -B/home/revitale/test_mainline_45/build/./prev-gcc/ -B/home/revitale/test_mainline_45/build/x86_64-unknown-linux-gnu/bin/ -B/home/revitale/test_mainline_45/build/x

Re: GCC's data dependence analyse may inaccuracy

Hello, > I unroll the following code one times in a gimpile pass. Can you please post the flags you used and the full test? I can try to reproduce this. Thanks, Revital

A question about loop-unroll

Hello, Is there a way to pass to the unroller the maximum number of iterations of the loop such that it can decide to avoid unrolling if the maximum number is small. To be more specific, I am referring to the following case: After the vectorizer decides to peel for alignment it creates three lo

A question regarding recognition of nop

Hello, Is there a general way to recognize a nop insn in RTL (using attributes?), or should I add a target hook for that? For example, I would like to recognize the following spu insn as a nop:?), (insn 555 210 203 11 (unspec_volatile [ (const_int 0 [0x0]) ] 14) 393 {lnop} (

A question about DCE

Hello, I want to emit the following SPU insn: emit_insn (gen_iorti3 (r77, tmp, GEN_INT(0))); r77 is defined as 'fixed register' which is a register that the register allocator can not use. (triggers by SPU option -mfixed-range) r77 is used to pass information to some other routine at run-time (

Re: A question about DCE

Hello, > > The problem is that r77 is not used in it's function after this instruction > > and thus DCE deletes it. > > Don't focus on DCE. That's not the problem; the fact that there's no > visible dependence is the problem. Can you make the next instruction > have a use for r77 explicitly (CAL

Re: Which target has working modulo scheduling?

[EMAIL PROTECTED] wrote on 17/10/2008 16:36:32: > Hello, > I tried to enable modulo scheduling for our target VLIW. It fails even for the > simplest loop. I would like to have a look at how GCC produces schedule for > other targets. I know that modulo scheduling relies on doloop_end pattern to >

Re: Inserting Custom RTLs by the Haifa Scheduler

Hello, > I am currently working on OpenRISC port of GCC-4.0.2, and I have to > insert a custom RTL (which gets translated to an instruction) at fixed > parts of the code. I have created the custom instruction (by modifying > RTL.DEF) and then put the appropritae constraints in my .md file. >

A question regarding emitting additional info to an insn

Hello, I want print additional information for each branch insn which will be used by the linker (for the SPU software i-cache), for example: brsl $lr,[EMAIL PROTECTED] and I wonder what is the best way to implement it in GCC. I defined a new note (in reg-notes.def) which can be attached to ea

A question about cleanup_cfg ()

Hello, I have a basic-block and I want to get the last jump insn of it. I use BB_END (bb) for that purpose. The instruction I get is a NOTE_INSN_PROLOGUE_END which appears right before the jump insn; and when doing NEXT_INSN for that note I get the first insn of the next bb (code_label); which me

[PATCH] SMS - Pass the actual schedulable rows to compute_split_row

Hello, > > Using testsuite/gcc.dg/sms-6.c as an example and compiling it for > PowerPC, > > node 18 (see attachment) is in a SCC and cannot be scheduled until > spliting > > twice. The MII = 20 and the schedule can only be found at II = 24. > > Yes, I see. This example raises a couple of issues:

ICE in ira.c

Hello, I get the following ICE while building gcc on CELL spu; trunk -r146825. (it passes OK on ppc) Thanks, Revital gcc -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wcast-qual -Wold-style-definition -Wc++-compat -Wmissing-form

Re: ICE in ira.c

Hello, > > Not really an ICE! Right, sorry about that. Looks like the code is assuming that all backends use at > least one define_register_constraint. (Also, there's a missing '\n' that > probably makes your generated definition of REG_CLASS_FROM_CONSTRAINT look a > bit odd!) How about some

error in gfc_simplify_expr

Hello, I get the following error while bootstrap trunk -r148275 on ppc. Thanks, Revital /home/eres/mainline_45/build/./prev-gcc/xgcc -B/home/eres/mainline_45/build/./prev-gcc/ -B/usr/local/powerpc64-unknown-linux-gnu/bin/ -B/usr/local/powerpc64-unknown-linux-gnu/bin/ -B/usr/local/powerpc64-unk

Re: Bootstrap failures on solaris

Hello, > i386-pc-solaris: > > cc1: warnings being treated as errors > /export/home/arth/gnu/gcc.git/gcc/tree-ssa-loop-prefetch.c: In function > 'loop_prefetch_arrays': > /export/home/arth/gnu/gcc.git/gcc/tree-ssa-loop-prefetch.c:1589:7: error: > format '%ld' expects type 'long int', but argument

Re: Unnecessary regmoves in modulo scheduler?

Hello Bingfeng, > I found a true register dependency is always accompanied with a cross-iteration > anti dependency. When -fmodulo-sched-allow-regmoves flag is set some anti-deps edges are not created. Please see add_cross_iteration_register_deps () function in ddg.c. HTH, Revital This should g

RE: Unnecessary regmoves in modulo scheduler?

egisters could be painful. Revital > > > -Original Message----- > > From: Revital1 Eres [mailto:e...@il.ibm.com] > > Sent: 23 June 2009 14:40 > > To: Bingfeng Mei > > Cc: Ayal Zaks; gcc@gcc.gnu.org > > Subject: Re: Unnecessary regmoves in modulo schedu

Re: Compiling gcc 4.4.0 for Cell

Hello, > I am trying to compile gcc 4.4.0 for the Cell processor for my google > summer of code project (GCC's OpenCL implementation starting point). > > I have used OpenMP for some things and now I am trying to compile > everything on the Cell. OpenMP is supported in the ppu-gcc 4.1.0 so > I am

A question regarding bundling and NOPs insertion for VLIW architecture

Hello, I have a question regarding the process of bundling and NOPs insertion for VLIW architecture and I appreciate your answer: I am calling the second scheduler from the machine reorg pass; similar to what is done for IA64. I now want to handle the bundling and NOPs insertion for VLIW archite

Help with expanding compare

Hello, I am using current mainline to compile a testcase which contains a loop. The target I'm working on supports cmpsi pattern. While expanding the loop condition I get that do_compare_rtx_and_jump () and do_jump_by_parts_greater_rtx () call each other repeatedly. The test I'm compiling pass

Re: Help with expanding compare

Hello, Just did so... :-) and it indeed solves this. Thanks, Revital From: Paolo Bonzini To: Revital1 Eres/Haifa/i...@ibmil Cc: gcc@gcc.gnu.org Date: 25/05/2010 03:57 PM Subject:Re: Help with expanding compare Sent by:Paolo Bonzini On 05/25/2010 12:13

Re: Question about Machine Description

Hello, > I want to limit the size of immediate field of some operation. I think you can look at SIGNED_INT_FITS_N_BITS definition at config/crx/crx.c for such example. You can write a predicate like the following; and use it when describing the immediate operand in the md file. (define_predicate

Help with reload

Hello, I have a question regarding code generation for a new target I'm working on. I am using GCC 4.6. In reload pass the following first instruction is replaced with the second one after spilling reg 182 to the stack. The problem is that the generated new instruction does not have a valid ad

A question about mov pattern

Hello, In the new target I'm working on there are branch regs and gprs. The loads and store instructions are only to/from the gprs, so if a branch reg needs to be spilled it first needs to be moved to a gpr and then stored to memory. I've implemented mov pattern in the machine description file f

A question about doloop

Hello, Doloop optimization fails to be applied on the following kernel from tescase sms-4.c with mainline (-r 162294) due to 'Possible infinite iteration case' message; taken from the loop2_doloop dump. (please see below). With an older version of gcc (-r 146278) doloop succeeded to be applied an

A question about MAX_EXPR

Hello, I'm compiling the following test with GCC 4.6.0 and I do not see that MAX_EXPR is generated for (num)<0)?0:(num). With GCC 4.3.2 it is generated OK in original dump (both compilation were made with -O3). Is there a flag I should use to generate MAX_EXPR with GCC 4.6.0? Thanks, Revital #

Question about Doloop

Hello, Doloop optimization fails to be applied on the following inner loop when compiling for PowerPC (GCC -r162294) due to: Doloop: number of iterations too costly to compute. I do not understand why as the number of iterations is max_cols and I appreciate an explanation. Thanks, Revital 1

Question about alias check in ddg.c

Hello, When trying to compile the following loop with GCC -r164298 with modulo scheduling pass enabled on PowerPC I get that the inter loop edges between the memory instructions are created in the DDG although the following check in ddg.c exists: static void add_inter_loop_mem_dep (ddg_ptr g, dd

A question about using restrict

Hello, I have the loop below and I want to pass to gcc that src1 and src2 never alias with dst; so I used the restrict keyword as below; however I still see that there are dependence edges between dst and src1 and src2 in the DDG created by SMS and I wonder how can I resolve this. (I used GCC -v1

RE: A question about using restrict

Hello Bingfeng, Thanks for your reply! I would be very interested to try your patch. Revital From: "Bingfeng Mei" To: Revital1 Eres/Haifa/i...@ibmil, "gcc@gcc.gnu.org" Date: 13/12/2010 12:20 PM Subject:RE: A question about using restrict

Re: [ARM] Implementing doloop pattern

ule for the loop we usually gain a speedup, and when SMS fails, we often have some slowdown, which have appeared because of do-loop conversion. The questions are: How to properly fix the ICE described? Do you think this approach (after the fixes) can make its way into trunk? Happy holidays! -- Ro

Re: [ARM] Implementing doloop pattern

Hello, > > @@ -162,6 +175,7 @@ doloop_condition_get (rtx doloop_pat) > return 0; > >if ((XEXP (condition, 0) == reg) > + || (REGNO (XEXP (condition, 0)) == CC_REGNUM) >|| (GET_CODE (XEXP (condition, 0)) == PLUS >&& XEXP (XEXP (condition, 0), 0) == reg)) >

A question concering GCC testsuite

Hello, I appreciate it if someone could explain what is the difference between gcc.c-torture library and gcc.dg library under the testsuite directory. Thanks, Revital

A question regarding -fwrapv flag

Hello, I am running the attached testcase (inspired from vect/vect-reduc-3.c testcase) with -O3 -fwrapv on powerpc64-linux with trunk 4.4. Here is a snippet from the testcase: ... unsigned short ub[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; unsigned short uc[N] = {0,1,2,3,4,5,6,7,

Bootstrap failure on powerpc64-linux

Hello, I get the following bootstrap failure on powerpc64-linux, trunk r132684 configure with: --with-cpu=default32 --enable-checking --enable-bootstrap Revital libtool: compile: /home/revitale/mainline_branch/build/./gcc/xgcc -B/home/revitale/mainline_branch/build/./gcc/ -B/home/revitale/ma

Re: Supporting 'MAC' instruction on gcc v4.1.1

[EMAIL PROTECTED] wrote on 11/05/2007 15:26:16: > Hello all, > > I am working on gcc v4.1.1 for a non-gcc target. I want to support > 'MAC' instruction > (mac OP1, OP2, OP3 => OP3 += OP1 * OP2). > http://gcc.gnu.org/ml/gcc/2007-05/msg00114.html seems relevant to your problem. Revital > > > R

Re: help required for upgradation of gcc-4.1.1

[EMAIL PROTECTED] wrote on 28/05/2007 09:05:24: > > Can you help to upgrade the gcc to 4.1.1 by providing the steps and > procedure etc I think you should try the gcc-help mailing list. Revital

Help in understanding ccp propagator

Hello, I will greatly appreciate any suggestions regarding the following problem I have with the ccp propagator. I am testing the new store ccp patch which propagates constants by walking the virtual use-def chain (http://gcc.gnu.org/ml/gcc-patches/2007-05/msg00055.html) and I encountered the fol

Re: Help in understanding ccp propagator

> > I will greatly appreciate any suggestions regarding the following > > problem I have with the ccp propagator. I am testing the new store > > ccp patch which propagates constants by walking the virtual use-def > > chain (http://gcc.gnu.org/ml/gcc-patches/2007-05/msg00055.html) and I > > encounte

Bootstrap failure on ppc64

Hello, The following error is received on ppc64. Thanks, Revital symtab.o -MT symtab.o -MMD -MP -MF .deps/symtab.Po ../../gcc/libcpp/symtab.c /home/eres/mainline_lim/build/./prev-gcc/xgcc -B/home/eres/mainline_lim/build/./prev-gcc/ -B/home/eres/mainline_lim/build/powerpc64-unknown-linux-gnu/bi

Re: Help in understanding ccp propagator

> I can modify it to catch it pretty easily, just walk back a few vuses > if the current set of vuses is defined by something that does not > actually touch our offset. This sounds like what I am trying to do in ccp... > > > > I am not sure I understand. The new patch uses the infrastructure of

Re: vector compare

> Could someone tell me how to do vector compare in generic way? AFAICT every target which supports vector operations has it's own list of built-in function for vector comparison. For example, Altivec has vec_cmpgt and other built-ins for vector compare instructions. (see altivec.h file for the

Help understanding tree-affine.c

Hello, I am trying to understand the usage of some functions in tree-affine.c file and I appreciate your help. For example; for the two memory accesses arr[b+8].X and arr[b+9].X, how does their affine combinations will look like after executing the following sequence of operation? (taken from

Re: Help in understanding ccp propagator

> The engine only knew how to propagate cases that always make the same > set of vdef/vuses, so it was safe to only tell it to use the first > vdef. > > /* Note that for propagation purposes, we are only interested in > visiting statements that load the exact same memory reference >

Creating new variable in tree level

Hello, I appreciate your help in figuring what is considered a valid sequence of operations for creating a new variable in the tree level. Is the following sequence OK - tmp_var = create_tmp_var (type, "_new_"); add_referenced_tmp_var (tmp_var); mark_sym_for_renaming (tmp_var); Or should I

Generating a phi node

Hello, I have two ssa vars (i0 and i1 in the following example); what is the sequence to generate a new phi node corresponding to i3 - if (...) i0 = exp1 else i1 = exp2 i3 = PHI(i0 , i1); Thanks, Revital

Re: Help in understanding ccp propagator

Hello, I have one more question regarding the comment in tree-ssa-ccp.c file - /* Note that for propagation purposes, we are only interested in visiting statements that load the exact same memory reference stored here. Those statements will have the exact same list

cp_compat_x_tst.o-cp_compat_y_tst.o testcase

Hello, While testing a patch on current trunk (r 125640) I've noticed that g++'s cp_compat_x_tst.o-cp_compat_y_tst testcase fails with unexpected failure on x86_64 with the vanilla version but passes OK with the patched version (-O2). On ppc64 and i486 the test passes both with the vanilla and t

Re: Gcc trees

[EMAIL PROTECTED] wrote on 21/06/2007 15:44:27: > Hello. i am Alberto > > I work with Gcc trees to modify c++ original code and dont find and i > need documentation about trees because the web isnt enought information. > > Where are docs about gcc trees and macros to access it? > In GCC wiki you

Bootstrap comparison failure on powerpc64 for Ada

Hello, I get the following bootstrap comparison failure on powerpc64 for Ada (--enable-languages=ada) with BOOT_CFLAGS='-O2'. Revital make[2]: Entering directory `/home/revital/mainline_ccp/build' make[3]: Entering directory `/home/revital/mainline_ccp/build' rm -f stage_current make[3]: Leavi

Re: Bootstrap comparison failure on powerpc64 for Ada

> Which revision? The Ada compiler bootstraps fine on i586 and x86-64 at > revision 125912:125915M (i.e with structural alias analysis enabled). > revision 125915. Thanks, Revital

Re: Bootstrap comparison failure on powerpc64 for Ada

> > > > Which revision? The Ada compiler bootstraps fine on i586 and x86-64 at > > revision 125912:125915M (i.e with structural alias analysis enabled). > > Note that if cc1-checksum.o differs, it likely means the issue is unrelated to > Ada. I am now bootstrapping only c. If that will pass OK

Re: Bootstrap comparison failure on powerpc64 for Ada

Eric Botcazou <[EMAIL PROTECTED]> wrote on 21/06/2007 21:10:15: > > I am now bootstrapping only c. If that will pass OK I can check Ada on > > an older revision if you wish. > > I'm not sure that would really help in this case. The fact that x86 and > x86-64 are both clean with structural alia

Re: Bootstrap comparison failure on powerpc64 for Ada

Eric Botcazou <[EMAIL PROTECTED]> wrote on 23/06/2007 21:50:57: > > I'm going to try the 64-bit variant. > > SPARC/Solaris 64-bit is OK, as well as IA-64/Linux according to: > http://gcc.gnu.org/ml/gcc-testresults/2007-06/msg01044.html > > Do you test PowerPC 32-bit or should I try a build on

Re: Bootstrap comparison failure on powerpc64 for Ada

[EMAIL PROTECTED] wrote on 24/06/2007 01:17:34: > > I tested it on powerpc64-linux with the default option > > --with-cpu=default32. > > Ah, so this is a 32-bit compiler like on sparc64-linux? --with-cpu=default32 means that the compiler itself and it's produced code are 32 bits by default. Re

Re: bootstrap broken on powerpc?

> checking whether the GNU Fortran compiler is working... no > configure: error: GNU Fortran is not working; please report a bug in > http://gcc.gnu.org/bugzilla, attaching > /Develop/mainline-dn/build3/powerpc64-unknown-linux-gnu/libgfortran/config.log > make[1]: *** [configure-target-libgfortran

Re: Ongoing bootstrap failures on ppc64 since 2007-07-02

> The newly built gfortran must be stomping on memory. I've found that > attached patch allows gfortran to still function. Could someone who > sees this problem try bootstrapping gfortran with the patch? I will try it. Revital

Re: Ongoing bootstrap failures on ppc64 since 2007-07-02

> The newly built gfortran must be stomping on memory. I've found that > attached patch allows gfortran to still function. Could someone who > sees this problem try bootstrapping gfortran with the patch? gfortran bootstrapped OK with this patch on ppc64 r126353. Thanks, Revital

ICE while bootstraping on ppc64.

Hello, The following ICE is received on r126521 while bootstraping on ppc64. Revital /home/eres/test_again/build/./gcc/xgcc -B/home/eres/test_again/build/./gcc/ -B/home/eres/test_again/build/powerpc64-unknown-linux-gnu/bin/ -B/home/eres/test_again/build/powerpc64-unknown-linux-gnu/lib/ -isystem

[PATCH] Modulo-scheduling improvements. Patch 1 of 2. - A status update

Hello, I wanted to update the status of the first patch that Vladimir had posted to improve modulo-schedualing. (http://gcc.gnu.org/ml/gcc-patches/2007-01/msg01468.html). I tested this patch on ppc64 and currently there is one difference in one of the fortran's testcases (forall_10.f90); this te

Summary of the BOF regarding the general policy of floating point arithmetic in GCC

Hello, The summary of the BOF regarding floating point arithmetic in GCC from the summit can be found in the following wiki page: http://gcc.gnu.org/wiki/FP_BOF Thanks, Revital

Re: Failure in bootstrapping GFortran 4.3.0 on Cygwin

Also on ppc64. Revital [EMAIL PROTECTED] wrote on 17/08/2007 09:55:38: > > I want to flag that some changes in GCC 4.3.0 20070816 rev 127568: > > * Makefile.in (REVISION): New. > (REVISION_c): New. > (REVISION_s): New. > (version.o): Also depend on $(REVISION). Ad

Re: gcc.dg/sms-antideps.c fails on IA64 (modulo scheduling problem)

[EMAIL PROTECTED] wrote on 18/08/2007 03:19:48: > I noticed that gcc.dg/sms-antideps.c is failing on my IA64 Linux and > HP-UX platforms. The failure is: > > x.c: In function 'foo': > x.c:25: internal compiler error: in gen_sub2_insn, at optabs.c:4640 > Please submit a full bug report, > with p

Build failure on ppc64

Hello, I get the following error on ppc64 with trunk r127835: c/gcc/. -I../../gcc/gcc/../include -I../../gcc/gcc/../libcpp/include -I../../gcc/gcc/../libdecnumber -I../../gcc/gcc/../libdecnumber/dpd -I../libdecnumber../../gcc/gcc/regclass.c -o regclass.o ../../gcc/gcc/regclass.c: In function

ICE in langhooks.c on SPU

Hello, I get the following ICE with trunk r127857 running the testsuite on SPU: :0: internal compiler error: in add_builtin_function, at langhooks.c:485^M Please submit a full bug report,^M with preprocessed source if appropriate.^M See for instructions.^M compiler

Re: ICE in langhooks.c on SPU

> Wow, you mean SPU has more builtins than x86_64? Up the bitfield > width of tree.h tree_function_decl.function_code until it no longer ICEs. > Changing the following indeed solves the problem: Index: tree.h === --- tree.h (r

Re: ICE in langhooks.c on SPU

[EMAIL PROTECTED] wrote on 28/08/2007 17:31:08: > On 8/28/07, Dave Korn <[EMAIL PROTECTED]> wrote: > > On 28 August 2007 15:10, Richard Guenther wrote: > > > > > > > > Or maybe on ppc/spu enum bitfields are signed and the following > > > > > > DECL_FUNCTION_CODE (decl) = -1; > > > gcc_asser

Error in c-lex.c

Hello, I get the following error running trunk r127993 with --enable-checking=assert on ppc64: gcc -c -g -fkeep-inline-functions -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -Wmissing-format-attribute-DHAVE_CONFIG_H -I. -I. -I../../gcc

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