For debugging, you can filter the offending file through something like
sed -e 's_^#line _// _' and recompile.
--
Rask Ingemann Lambertsen
a value in a data register
sets the condition codes while storing a value in an address register leaves
the condition codes unmodified. A fourth possibility is that of the PowerPC,
where this is optional on a per insn basis, but then you wouldn't normally
include the (clobber (reg:CC 21 cc)) version in the machine description.
--
Rask Ingemann Lambertsen.
ng reloads to be
sorted in the wrong order (see reload_reg_class_lower() in reload.c),
thereby exhausting a small register class.
> Can i disable filling/spilling for this register class?
-ffixed-name_of_register
--
Rask Ingemann Lambertsen
ite normal for the first 6-7 dump files. It is because matching
has not yet been attempted.
--
Rask Ingemann Lambertsen
ilogue
code too, -fdump-rtl-rnreg.
--
Rask Ingemann Lambertsen
-fdump-rtl-all-details will give you an idea of how far the compiler
gets, and thus maybe a clue to which pass runs into problems. Also, a
backtrace from the debugger is nice to have.
--
Rask Ingemann Lambertsen
debug_rtx (stack_pointer_rtx)
And btw, which GCC version?
--
Rask Ingemann Lambertsen
On Mon, Oct 02, 2006 at 12:42:04PM +0200, Wolfgang Mües wrote:
> Now it's time to give a big "thank you" to all persons involved,
> ecpecially Rask Ingemann Lambertsen with his invaluable help.
>
> As I started this project, I feared that I would never succeed,
scribes the procedure for appointing
maintainers. Not having this clearly documentaion will easily cause
confusion because people who are not maintainers but have "write after
approval" permission are also listed in a file called MAINTAINERS, where
they are even supposed to add themselves.
--
Rask Ingemann Lambertsen
support, but
grep for LONG_TYPE_SIZE and LONG_LONG_TYPE_SIZE in the .h file and compare
the two.
--
Rask Ingemann Lambertsen
iler that is creating the wrong code and then see if you
> can guess why.
I usually diff the dump files. If your screen is wide enough, a side by
side diff can help you a lot for small functions.
--
Rask Ingemann Lambertsen
e_expand for movdi that is not reload safe.
And in case the target doesn't have registers capable of holding DImode
values, consider deleting the movdi pattern.
--
Rask Ingemann Lambertsen
See e.g.:
>
> http://gcc.gnu.org/ml/gcc/2003-04/msg01397.html
> http://gcc.gnu.org/ml/gcc/2004-06/msg00993.html
PR number?
--
Rask Ingemann Lambertsen
extern void getit (void **arg);
int main ()
{
int *foo;
void *bar;
getit (&bar);
memcpy (&foo, &bar, sizeof (foo));
printf ("foo: %x\n", *foo);
return (0);
}
--
Rask Ingemann Lambertsen
x27;t enough, try adding an expander also:
(define_expand "rotlhi3"
[(set (match_operand:HI 0 "register_operand")
(rotate:HI (match_operand:HI 1 "register_operand")
(match_operand:HI 2 "const_int_operand")))]
""
{
if (INTVAL (operands[2]) != 8)
FAIL;
})
--
Rask Ingemann Lambertsen
On Sun, Nov 19, 2006 at 08:31:22AM -0700, Eric Weddington wrote:
> Rask, do you have FSF paperwork in place?
Yes, it was completed recently.
--
Rask Ingemann Lambertsen
) << 16);
t.d[0] = BSWAP_16 (t.d[0]);
return (t.x);
}
/*
bswap_32_b:
movl4(%esp), %edx
movl%edx, %eax
rolw$8, %ax
movw%ax, %dx
movl%edx, %eax
roll$16, %eax
movl %eax, %edx
rolw$8, %ax
movw%ax, %dx
movl%edx, %eax
ret
*/
--
Rask Ingemann Lambertsen
internal compiler error: in rtl_verify_flow_info, at
> cfgrtl.c:2065
Does this patch
http://gcc.gnu.org/ml/gcc-patches/2006-11/msg01239.html> fix it?
--
Rask Ingemann Lambertsen
call subreg_regno_offset (xregno=8, xmode=SImode, offset=2, ymode=HImode)
which is fine and returns 1.
--
Rask Ingemann Lambertsen
On Mon, Nov 27, 2006 at 02:21:36PM -0800, Ian Lance Taylor wrote:
> Rask Ingemann Lambertsen <[EMAIL PROTECTED]> writes:
>
> >If I take out the lines 5643 and 5644
> >
> > if (regno < FIRST_PSEUDO_REGISTER)
> >
8/3
rts
where
move.l 4(%sp), %d1
lsl.b %d1,x
rts
should have been generated. Also, notice the redundant zero extension.
Why are we not generating a QImode shift instruction?
--
Rask Ingemann Lambertsen
0.
This is not true on i386 and m68k.
--
Rask Ingemann Lambertsen
On Sun, Dec 17, 2006 at 09:40:15PM +0100, Rask Ingemann Lambertsen wrote:
>Similarily for m68k,
[cut]
> where
>
> move.l 4(%sp), %d1
> lsl.b %d1,x
> rts
>
> should have been generated.
I'm sorry, please forget that. 8-bit shifts a
] == 2) return 1;
> return 0;
> }
No, because you'd read past the end of the array:
#include
int main (int argc, char *argv[])
{
char *a;
if ((a == malloc (sizeof (char
{
int r;
a[0] = 1;
r = f (a);
free (a);
return (r);
}
return (0);
}
--
Rask Ingemann Lambertsen
On Sat, Dec 23, 2006 at 10:06:54AM +0100, Rask Ingemann Lambertsen wrote:
> a[0] = 1;
Oops, that should be a[0] = 0 or any other value than 1.
--
Rask Ingemann Lambertsen
On Wed, Jan 03, 2007 at 11:28:29PM -0500, Daniel Jacobowitz wrote:
> Hopefully, this will not have any great impact on much of anyone.
It does. It fixed PR target/30370 (libgcc failing to build on
powerpc-unknown-eabispe) on mainline.
--
Rask Ingemann Lambertsen
y, go ahead and submit them.
--
Rask Ingemann Lambertsen
nt not to close the bug as fixed in that
case. Which is what happened, unfortunately.
--
Rask Ingemann Lambertsen
timerstruct->callbackfunc (...);
...
}
so be careful when implementing such warnings.
--
Rask Ingemann Lambertsen
anch just isn't always the one at
svn://gcc.gnu.org/svn/gcc/trunk. You basicly can't prevent people from
implementing new features. It will inevitably be the case that some people
will focus more on adding new features than on fixing bugs and vice versa.
--
Rask Ingemann Lambertsen
ode in order to contribute my
> development. I would appreciate any help. By the way, I already had a
> look in the GCC Internals manual but I am still a bit confused.
I would like to encurage you to submit a patch for the GCC Internals
manual to make it clearer.
--
Rask Ingemann Lambertsen
...
I'd try changing operand 2 of andhi3 from general_operand to
splitable_operand, because none of the andhi3 insn patterns seem to match
(set (reg:HI) (and:HI (reg:HI) (mem:HI (mem:HI .... In particular,
*andhi3_gen needs operand 2 to be a splitable_operand, which (mem:HI (mem:HI
...)) is not.
--
Rask Ingemann Lambertsen
whole
gcc command line in a target makefile fragment?
--
Rask Ingemann Lambertsen
what? Libgcc used to build fine without decimal float support.
--
Rask Ingemann Lambertsen
On Sun, Jan 21, 2007 at 02:00:06PM -0500, Daniel Jacobowitz wrote:
> On Sat, Jan 20, 2007 at 01:15:19PM +0100, Rask Ingemann Lambertsen wrote:
> >Somewhere in the libgcc build machinery, there is mechanism to override
> > the default LIBGCC2_UNITS_PER_WORD setting when compilng
See also http://gcc.gnu.org/ml/gcc-patches/2006-12/msg00241.html>.
You probably need to be prepared, whatever that means, for
HARD_REGNO_NREGS() to be called with parameters for which
HARD_REGNO_MODE_OK() returns 0. As you've found out, subreg_get_info() might
do that.
--
Rask Ingemann Lambertsen
ed earlier this month at
http://gcc.gnu.org/ml/gcc-patches/2007-01/msg00600.html>. I have
regrettably forgotten to ping this patch (for which I think David's approval
was only for the 4.2 branch). In any case, I don't have SVN write access and
will need someone else to commit the patch.
--
Rask Ingemann Lambertsen
ably not what you want (although reload will handle the third
example. Notice how I omit the word "fine" here). You need to read about
operand predicates and insn conditions.
--
Rask Ingemann Lambertsen
t; "1")])
>
> Instruction canonicalization doesn't work, since as explained in
> http://gcc.gnu.org/onlinedocs/gccint/Insn-Canonicalizations.html
> it only works if the second operand is a constant.
It is not clear what isn't being canonicalized. Please provide an example
of an insn which isn't canonical and what it should look like canonicalized.
--
Rask Ingemann Lambertsen
for the second operand. */
int
commutative_operand_precedence (rtx op)
{
enum rtx_code code = GET_CODE (op);
/* Constants always come the second operand. Prefer "nice" constants. */
if (code == CONST_INT)
return -7;
[...]
The comment disagrees with the code.
--
Rask Ingemann Lambertsen
GCC currently generates for
void mystrcpy (char *dest, char *src)
{
while ((*dest++ = *src++))
;
}
but the loop should compile to (a1 = dest, a0 = src)
Loop:
move.b (a0)+, (a1)+
bne.s Loop
at least for -Os or -mtune=68010.
--
Rask Ingemann Lambertsen
re
involved, e.g.
(set (subreg:SI (reg:DI T) 0) (mem:SI addr))
(set (subreg:SI (reg:DI T) 4) (mem:SI addr+4))
For example, I don't know how to make this work with adjecent structure
fields. You could try to extend the optimization that GCC already does for
loading adjecent structure fields smaller than a word; the one enabled by
SLOW_BYTE_ACCESS.
--
Rask Ingemann Lambertsen
isters when GCC is targeted at a processor with 32-bit registers.
Btw, this is no longer true unless you pass -fno-split-wide-types.
--
Rask Ingemann Lambertsen
(operands[0])"
"#"
"reload_completed"
...
but looking at recog.c, sure enough: general_operand() doesn't accept the
(concat ...) construct. Is that intentional?
--
Rask Ingemann Lambertsen
On Wed, Apr 25, 2007 at 09:11:52AM -0700, Richard Henderson wrote:
> On Wed, Apr 25, 2007 at 01:51:34PM +0200, Rask Ingemann Lambertsen wrote:
> > (define_mode_macro GT16 [SI DI TI SF DF XF SC DC XC SD DD TD CHI CSI CDI
> > CTI])
> >
> > (define_insn_and_split "*
On Thu, Apr 26, 2007 at 01:52:37PM -0700, Richard Henderson wrote:
> On Thu, Apr 26, 2007 at 09:49:16PM +0200, Rask Ingemann Lambertsen wrote:
> >Unfortunately, the fallback code isn't exactly optimum, as it produces
> > something like
> >
> > addw
On Fri, Apr 27, 2007 at 08:24:11AM -0700, Richard Henderson wrote:
> On Fri, Apr 27, 2007 at 04:00:13PM +0200, Rask Ingemann Lambertsen wrote:
> >I don't see how emit_move_complex_push() can ever generate a push
> > instruction. Here's a backtrace:
>
> emit_
ot;
code. I'll try to find a fix.
--
Rask Ingemann Lambertsen
]).
That will work. I have "e" (think of %eax) for that purpose.
[snip patches]
> Of course these patches almost certainly only appear to fix my
> *immediate* problem. "The problem" being that I want to be able to tell
> GCC two different things: "I want %dx to b
REGNO (SUBREG_REG (out))),
+SUBREG_BYTE (out),
+REGNO (SUBREG_REG (out)), GET_MODE (out)),
VOIDmode, VOIDmode, 0, 0,
opnum, RELOAD_OTHER);
}
Comments will be appreciated. It would also be very interesting to see
how this works on the m32c, in particular.
Best regards,
Rask Ingemann Lambertsen
Even a pushm1 pattern
(see "Standard Pattern Names for Generation") is not necessary if you are
happy with the code that GCC itself comes up with.
--
Rask Ingemann Lambertsen
s of reload over the last five
months and still don't understand many parts of it, but I'll help you with
those parts that I do understand.
> The information I found in the gcc
> internals docs and other parts of the inet are pretty widespread. I would be
> glad if some
UIRED and ELIMINABLE_REGS. You want the
former to be 0 and the latter to contain an elimination of
FRAME_POINTER_REGNUM into STACK_POINTER_REGNUM. Also check
CAN_DEBUG_WITHOUT_FP.
[not making BP fixed]
> Can I do the same thing with SP?
I don't know. The difficulty is somewhere between nontrivial and impossible.
Don't try this at first.
--
Rask Ingemann Lambertsen
])
(const_int 8 [0x8])
(const_int 8 [0x8]))
which seems to be the simplest way of saying "zero extend byte 1 of
register 22 to 16 bits".
Also, is there a function for simplifying a zero_extract?
--
Rask Ingemann Lambertsen
posed to have a dependency on insn 12.
There is no overlap between the subregs. I would have thought that insn 13
should have a dependency on insn 6, 7 and possibly 14, like insn 12.
Am I simply misunderstanding the purpose of (undocumented) REG_DEP_TRUE?
--
Rask Ingemann Lambertsen
ked up by combine.
There is a lot of simplification code in combine.c too. Should I try to add
these simplifications to both combine.c and simplify-rtx.c?
--
Rask Ingemann Lambertsen
g it wrong. So I'll put a breakpoint there and
see what happens.
--
Rask Ingemann Lambertsen
[cut]
The problem is that line numbers larger than 32767 are only supported with
C99 or better, which we don't request from gcc. Because of -pedantic, GCC
complains. Suggestions are welcome.
i386.md is more than 2 lines long, btw.
--
Rask Ingemann Lambertsen
at least be able to get
your compile going by telling GCC to return the value in memory instead.
I don't recall exactly how this is done - my i8086 backend returns anything
larger than 32 bits in memory - but see the sections "How Scalar Function
Values Are Returned" and "How Large Values Are Returned".
--
Rask Ingemann Lambertsen
9,7 +1049,7 @@
{
printf ("case CONSTRAINT_%s:\n return ", c->c_name);
write_predicate_expr (c->exp);
- fputs (";\n\n", stdout);
+ fputs (";\nLINE\n\n", stdout);
}
puts ("default: break;\n"
Index: gcc/genrecog.c
===
--- gcc/genrecog.c (revision 112877)
+++ gcc/genrecog.c (working copy)
@@ -2129,6 +2129,7 @@
case DT_c_test:
print_c_condition (p->u.c_test);
+ puts ("\nLINE");
break;
case DT_accept_insn:
--
Rask Ingemann Lambertsen
,%0")
Operand 1 should have a predicate of "nonimmediate_operand" and a constraint
of "rm".
Also, aren't the segment registers HImode registers? Above, you wrote:
>register short a __asm__ ("es");
^
And have you adjusted HARD_REGNO_MODE_OK() and HARD_REGNO_NREGS() accordingly?
--
Rask Ingemann Lambertsen
ot;general_operand" "=s")
>(match_operand:SI 1 "register_operand" ""))]
>""
>"movl\t%1,%0")
I think you'll have to add "s" alternatives to the *movhi pattern instead of
adding two new patterns, since otherwise there will be two nearly identical
patterns and GCC might use the wrong one. If you need patterns named
"store_seg" and "load_seg", use an expander.
--
Rask Ingemann Lambertsen
ction to be generated automatically, so that
you can call it from a (define_expand ...). FWIW, I'm using '_' for this
purpose. It is permitted in C function names and makes a clash with future
standard pattern names unlikely.
Just my DKK 0.02 worth.
--
Rask Ingemann Lambertsen
4 d))
(set (mem:HI stack-slot-a) (reg:HI 2 a))
(set (reg:HI 2 a) (mem:HI stack-slot-d))
(parallel [(set (reg:HI 2 a)
(mult:HI (reg:HI 2 a) (reg:HI 6 b)))
(clobber (reg:HI 4 d))
(clobber (reg:CC CC_REG))]
(set (reg:HI 0 c) (reg:HI 2 a))
(set (reg:HI a) (mem:HI stack-slot-a))
(set (reg:HI d) (mem:HI stack-slot-d))
What am I missing?
--
Rask Ingemann Lambertsen
, (register is globbered)
> and of course making the swpb call..
I think you will need to remove the '+' as already suggested and add
(clobber (match_scratch:QI "=X,X,X,1")) to tell GCC that the register
allocated to operand 1 is clobbered by the instruction for this particular
alternative. You will also have to modify any code which expands this
pattern accordingly.
--
Rask Ingemann Lambertsen
t a fixed register
(see FIXED_REGISTERS), refer to this register directly in the output template
and don't add a clobber to the movqi patterns. IMHO, that's an acceptable hack
at an experimental stage. If the resulting code runs correctly on the DS, you
can then undo the FIXED_REGISTERS change and add the clobber statements.
--
Rask Ingemann Lambertsen
On Sun, Jun 04, 2006 at 12:31:08PM +0200, Wolfgang Mües wrote:
> Hello Rask,
>
> On Friday 02 June 2006 09:24, Rask Ingemann Lambertsen wrote:
> > There may be a faster way of seeing if the modification is going to
> > work for the DS at all. I noticed from the output temp
byte loads and stores when generating code.
--
Rask Ingemann Lambertsen
orary register.
See TARGET_SECONDARY_RELOAD in the section "Register Classes".
> According to the manual, mov insns are not supposed to clobber a
> register.
I can't find any statement to that effect. Where does it say so? But I can
see why it would be a problem when r
str%?b\\t%1, %0"
> > [(set_attr "type" "*,*,load1,store1")
> >(set_attr "predicable" "yes")]
> > )
I think you should go back to this (i.e. the unmodified version) and only
change the "m" into "Q" in the fourth alternative of operand 0. See if that
works, i.e. generates addresses that are valid for the swp instruction. If
it does, then begin to add other changes.
--
Rask Ingemann Lambertsen
On Tue, May 30, 2006 at 08:23:34PM +0200, Rask Ingemann Lambertsen wrote:
> Hi.
>
> I have problems figuring out why reload gives up on this:
>
> reload failure for reload 1
> ../../../cvssrc/gcc/gcc/libgcc2.c: In function '__moddi3':
> ../../../cvssrc/gcc/gcc/l
@ lr needed for prologue
strbr1, [r0, #5]
str ip, [r0, #8]
str r3, [r0, #0]
bx lr
With -O2 -mswp-byte-writes:
bytewritetest:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
str lr, [sp, #-4]!
add r2, r0, #4
add lr, r0, #5
ldrbr3, [lr, #0]@ zero_extendqisi2
ldrbr1, [r2, #0]@ zero_extendqisi2
eor r2, r1, r3
add r3, r3, r1
ldr ip, [r0, #0]
str r3, [r0, #0]
swpbr3, r2, [lr, #0]
str ip, [r0, #8]
ldr pc, [sp], #4
The register allocator chooses to use the lr register, in turn causing link
register save alimination to fail, which doesn't help.
--
Rask Ingemann Lambertsen
temporary measure.
> I just
> wasn't sure from the thread whether you realised that output reloads
> might be a specific problem.
I was not aware of this. It is only the second time I've seen postreload
complain about unsatisfied constraints. Thanks for pointing out this
problem.
--
Rask Ingemann Lambertsen
On Tue, Jun 06, 2006 at 07:42:20AM +0200, Wolfgang Mües wrote:
> Rask,
>
> On Monday 05 June 2006 16:16, Rask Ingemann Lambertsen wrote:
> > I think the comment in arm.h is wrong. The manual seems to agree with
> > the code.
>
> Just to make it easy for beginners
On Tue, Jun 06, 2006 at 08:27:10PM +0200, Rask Ingemann Lambertsen wrote:
> On Tue, Jun 06, 2006 at 10:39:46AM +0100, Richard Sandiford wrote:
> > This is just a guess, but the insn above might be an output reload.
>
> It is, in a peculiar (and not useful) way. Diffing the gr
ded = 0, uses_anonymous_args = 0
@ link register save eliminated.
ldr r0, .L8
@ lr needed for prologue
ldrbr1, [r0, #0]@ zero_extendqisi2
mov r2, #134217728
.L2:
ldr r3, .L8+4
swpbip, r1, [r2, #0]
add r2, r2, #1
On Fri, Jun 02, 2006 at 09:24:17AM +0200, Rask Ingemann Lambertsen wrote:
> The rest of the ARM backend presently assumes that the pattern has the form
>
> (set (operand:QI 0) (operand:QI 1))
>
> but now we've changed it to
>
> (parallel [(set (operand:QI 0) (operand:
tion. Some sort of clue is given by
http://gcc.gnu.org/onlinedocs/gccint/Insn-Canonicalizations.html> but
is not the whole story.
--
Rask Ingemann Lambertsen
gister_operand" "r")
> (sign_extend:DI (match_operand:SI "register_operand"
> "r"]
> ...
> )
My first bet would be to place the sign_extend operand first of the two
operands to plus.
Also, the output from -fdump-rtl-combine will tell you if combine is
rejecting the pattern because the cost is too high.
--
Rask Ingemann Lambertsen
t the memory access
available in GO_IF_LEGITIMATE_ADDRESS(), such as the direction (read, write
or modify) and the insn (code number?) and operand number in which the
memory access occurs.
--
Rask Ingemann Lambertsen
and emit the
(f)emms instruction in the epilogue if an MMX register was ever used.
--
Rask Ingemann Lambertsen
sn (rtx x, rtx y)
{
- return emit_insn (gen_rtx_SET (VOIDmode, x, y));
+ if (general_operand (y, GET_MODE (x))
+return emit_move_insn (x, y);
+ else
+return emit_insn (gen_rtx_SET (VOIDmode, x, y));
}
/* Return the number of bits set in VALUE. */
--
Rask Ingemann Lambertsen
-patches/2006-03/msg01311.html>.
On http://gcc.gnu.org/lists.html>, please read the part which
follows: "Please do not include or reference confidentiality notices".
--
Rask Ingemann Lambertsen
bit
targets suffer from this much of the time. I can only imagine that the AVR
camp must be tearing their hair out in frustration. The register allocater
really needs to be able to allocate subregs independently.
--
Rask Ingemann Lambertsen
On Wed, Jul 19, 2006 at 01:24:59PM +0200, Rask Ingemann Lambertsen wrote:
>
> The function named emit_move_insn() ought to do the trick here, but
> is perhaps a bit heavyweight for this purpose. Anyway, try this patch
> (untested), which should plug this particular hole:
There was a
lly used, so it would
> seem to be treated the same as SImode. The target machine doesn't have
> special instructions for manipulating 24-bit pointers, all pointer moves
> and arithmetic are done with 32-bit instructions.
OK, use SImode.
--
Rask Ingemann Lambertsen
e, operands[2], DImode, 4);
/* If necessary, reload the address. */
if (REG_P (XEXP (operands[0], 0)))
{
operands[5] = operands[4];
operands[6] = operands[0];
}
else
{
operands[5] = XEXP (operands[0], 0);
operands[6] = gen_rtx_MEM (QImode, operands[4]);
}
})
(Is it OK to use gen_rtx_MEM() during reload? Should I use
replace_equiv_address() instead?)
--
Rask Ingemann Lambertsen
On Wed, Jun 07, 2006 at 07:22:31AM +0200, Wolfgang Mües wrote:
> On Tuesday 06 June 2006 21:33, Rask Ingemann Lambertsen wrote:
>
> > Yet another register which stands a good chance of being reusable is
> > the register containing the address.
>
> Yes, but that is not
On Thu, Jul 20, 2006 at 03:27:49PM +0200, Rask Ingemann Lambertsen wrote:
> (define_expand "reload_outqi"
> [(clobber (match_operand:QI 0 "memory_operand" "=Q"))
>(clobber (match_operand:DI 2 "register_operand" "=&r"))
&g
On Thu, Jul 20, 2006 at 04:37:41PM +0200, Rask Ingemann Lambertsen wrote:
> ;; This is primarily a hack for the Nintendo DS external RAM.
> (define_insn "_arm_movqi_insn_swp"
> [(set (match_operand:QI 0 "reg_or_Qmem_operand" "=r,r,r,Q,Q")
> (match_
yses/analysis/
--
Rask Ingemann Lambertsen
ld[i].opnum] and in case of a "0"
constraint, I'm sure it is possible to find the matching operand too
somehow. Then that information can be used to ensure rld[i].mode is large
enough. Is there any reason that operand_mode[] would not be reliable?
--
Rask Ingemann Lambertsen
On Fri, Aug 04, 2006 at 02:30:34AM +0200, Rask Ingemann Lambertsen wrote:
> The constraints are not met because the constraint "d" is register class
> DX_REGS consisting of register 4 and 5, and (reg:HI 5 dh) spans register 5
> and 6. Also, HARD_REGNO_NREGS (5, HImode) returns
ters which can't hold QImode values. They
are 16-bit only (%si, %di, %bp and %sp). Is there an undocumented assumption
here that if CANNOT_CHANGE_MODE_CLASS() returns true, then the number of hard
regs used is unchanged?
I haven't heard of REG_CANNOT_CHANGE_MODE_P before, and it i
)
(subreg:QI (reg:HI 643) 0)) 34 {movqi} (insn_list:REG_DEP_TRUE 2483
(nil))
(expr_list:REG_DEAD (reg:HI 643)
(nil)))
But nice try anyway, combine. :-)
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Rask Ingemann Lambertsen
these problems are creating an endless story, and sorry for
> generating traffic on this list, because I'm still no gcc expert...
You shouldn't be sorry about that. GCC provides a good, solid foundation
for learning something new every day.
> On the other hand, the compiler now has generated code from hundreds of
> files, and maybe I'm very near to success now.
I think so too.
--
Rask Ingemann Lambertsen
5 [0xf]))) 31 {*ashrhi3_const15}
(insn_list:REG_DEP_TRUE 2480 (nil))
(nil))
(insn 2605 2485 2486 39 libgcc2.c:1825 (set (mem/c:QI (plus:HI (reg/f:HI 10 bp)
(const_int -42 [0xffd6])) [10 S1 A8])
(reg:QI 4 d)) 34 {movqi} (nil)
(nil))
--
Rask Ingemann Lambertsen
"
(const_int -1 [0x])))
]) 68 {*dechi2_cc_ccz} (nil)
(nil))
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Rask Ingemann Lambertsen
prop?
No, because insn 96, which reads reg 32, might be executed the next time
through the loop.
--
Rask Ingemann Lambertsen
On Sun, Aug 13, 2006 at 10:16:02PM +0200, Rask Ingemann Lambertsen wrote:
> Note that right after expand, we have:
>
> (note 91 90 0 NOTE_INSN_BASIC_BLOCK)
>
> ;; size = size - 1
> (insn 93 91 96 (set (reg:HI 42)
> (const_int -1 [0x])) -1 (nil)
> (n
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