in a GCC port to a 16 bit cpu that uses CC flags for branching,
I'm experimenting with using a 32 bit subtract for compare
instead of multiple 16 bit compares and branches.
my cbranch4 expander produces a compare and conditional
branch patterns...
cmpmode = SELECT_CC_MODE( branchCode, op0,
);
emit_insn( gen_rtx_SET( VOIDmode, flags, compare ));
Sorry for the bother...
On 31/07/15 08:39, Paul Shortis wrote:
in a GCC port to a 16 bit cpu that uses CC flags for branching, I'm
experimenting with using a 32 bit subtract for compare instead of
multiple 16 bit compares and branches.
my cbr
I'm working with a CPU having a restricted set of registers that can do
three address maths wheres ALL registers can do two address maths.
If I define
(define_insn "addsi3"
[ (set (match_operand:SI 0 "register_operand" "=r,r")
(plus:SI (match_operand:SI 1 "register_o
arage any alternatives in the patterns.
Paul.
On 04/08/15 06:00, Jim Wilson wrote:
On 07/30/2015 09:54 PM, Paul Shortis wrote:
Resulting in ...
error: unable to find a register to spill in class ‘GP_REGS’
enabling lra and inspecting the rtl dump indicates that both
alternatives (R and r) seem
I'm porting gcc to a 16 bit cpu with a two address ISA like x86.
When using LRA I was getting compiler crashes and results like
this from the reload pass
(insn 97 96 98 21 (parallel [
(set (reg/f:HI 3 r3 [59])
(plus:HI (reg/f:HI 6 sp)
(const_int
I've now confirmed this same issue occurs on a stock i386 build
when -fomit-frame-pointer is specified with -O2 and a test case
with reasonable register pressure.
On 28/04/14 07:47, Paul Shortis wrote:
I'm porting gcc to a 16 bit cpu with a two address ISA like x86.
When using
For a 16 bit CPU the cmpelim pass is changing
(insn 33 84 85 6 (parallel [
(set (reg:HI 1 r1)
(ashift:HI (reg:HI 1 r1)
(const_int 1 [0x1])))
(clobber (reg:CC_NOOV 7 flags))
]) ../gcc/testsuite/gcc.c-torture/execute/960311-3.c:18
false;
in_a = SET_SRC (x);
Cheers, Paul.
On 05/09/14 02:33, Richard Henderson wrote:
On 09/03/2014 03:14 PM, Paul Shortis wrote:
(insn 33 84 85 6 (parallel [
(set (reg:HI 1 r1)
(ashift:HI (reg:HI 1 r1)
(const_int 1 [0x1])))
(cl
Correction,
...compare:CC_N... (R1:HI, 0)
On 05/09/14 09:31, Paul Shortis wrote:
Thanks Richard,
I found the bug. try_eliminate_compare follows register
definitions between the flags use and the clobbering compare by
register number only, i.e. the register width isn't considered.
I've ported GCC to a small 16 bit CPU that has single bit shifts.
So I've handled variable / multi-bit shifts using a mix of inline
shifts and calls to assembler support functions.
The calls to the asm library functions clobber only one (by
const) or two (variable) registers but of course call
On 02/02/15 18:55, Yury Gribov wrote:
On 01/30/2015 11:16 AM, Matthew Fortune wrote:
Yury Gribov writes:
On 01/29/2015 08:32 PM, Richard Henderson wrote:
On 01/29/2015 02:08 AM, Paul Shortis wrote:
I've ported GCC to a small 16 bit CPU that has single bit
shifts. So
I've handle
On 03/02/15 09:14, Joern Rennecke wrote:
On 2 February 2015 at 21:54, Paul Shortis wrote:
I could have avoided the expander and used a single instruction pattern for
a)b)c) if if could have found a way to have alternative dependent clobbers
in an instruction pattern. I investigated attributes
I'm porting gcc to a 16 bit processor. Occasionally compiling
source such as
short v1;
long global;
global = (long)v1;
results in ...
(insn 11 10 12 2 (set (subreg:HI (mem/c:SI (symbol_ref:HI
("global") ) [2 global+0 S4 A16]) 2)
(const_int 0 [0])) t.c:15 -1
(nil))
(insn
Thanks Richard,
That worked just as you suggested, and ... when I removed my
zero_extendhisi2 the IIRC the target-independent optabs code
generated exactly the same sequence.
Interestingly, I noticed that changing from my define_insn
"zero_extendhisi2" back to the define_expand "zero_extendh
Solved... kind of.
*ldsi is one of the patterns movsi is expanded to and as the name
suggests it only handles register loads. I know that at some
stages memory references will pass the register_operand predicate
so I changed the predicate for operand 0 and added an alternative
to *ldsi that c
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