I've ported gcc to a 16 bit CPU and have all torture tests
passing bar one, pr52286.c
The offending lines of code are
long a, b = 0;
asm ("" : "=r" (a) : "0" (0));
which should cause zero to be assigned to the "a" SI sized variable.
Inspecting the generated code revealed that zero was on
asking another issue.
Thanks again everyone... Paul.
On 29/08/17 04:01, Michael Matz wrote:
Hi,
On Mon, 28 Aug 2017, Paul S wrote:
I've ported gcc to a 16 bit CPU and have all torture tests passing bar one,
pr52286.c
The offending lines of code are
long a, b = 0;
asm ("" : &
I've been trying off and on for a couple of days to create a machine
description that handles the following target and produces the output I
am hoping for.
The CPU has a 16 bit word size - and only has word size registers. As a
consequence it sign or zero extends when loading byte operands -
Thanks Richard,
The penny dropped when I read your comment about the % operator. item
(2) send me back to the gcc internals document (again !) and I had the
problem sorted in about half an hour.
Thanks again,
Paul.
On 06/01/12 08:23, Richard Henderson wrote:
On 01/05/2012 10:33 PM, Paul S
g
set = single_set (insn);
on the parallel [plus:compare] operation and not finding the compare:CC
sub-operation because the plus::HI operation doesn't include a DEAD_REG
note (and I can't see that it should).
I'm clearly missing something... can anyone provide a hint ?
Paul S
gcc_internals.pdf of any special meaning assigned to the <> notation.
In any case - thanks again, with this blocker cleared I can proceed with
lower stress levels :-)
Cheers, Paul.
On 17/01/12 15:19, Hans-Peter Nilsson wrote:
On Mon, 16 Jan 2012, Paul S wrote:
In the port I&#
Thanks Dave,
I would never have guessed from gccinternals.pdf that it is possible to
use mode iterators to select predicates & constraints ... I think I have
a use for this today :-)
Cheers, Paul.
On 20/01/12 10:26, Dave Korn wrote:
On 17/01/2012 21:16, Paul S wrote:
For example
Happy to oblige, when I believe I'm competent to advise others :-)
On 23/01/12 14:21, Hans-Peter Nilsson wrote:
On Mon, 23 Jan 2012, Paul S wrote:
Thanks Dave,
I would never have guessed from gccinternals.pdf that it is possible to use
mode iterators to select predicates& co
Thanks,
I was mistakenly only considering ports that defined
TARGET_FIXED_CONDITION_CODE_REGS
Paul.
On 23/01/12 11:23, Richard Henderson wrote:
On 01/18/2012 08:16 AM, Paul S wrote:
Thanks H-P,
That worked first time !
For a few days I had been searching the non cc0 ports for hints
When generating code for a two address machine (like x86) I'm
trying to peephole sequences for commutative operations like
(destination registers on left)
1.addRm,Rn
2.ld Rn,Rm
to
1. addRn,Rm
I have defined this peephole2
define_peephole2
[
(parallel
I'm porting gcc 4.6.2 to a 16 bit CPU that has four GP registers. I've
chosen to allocate R3 as the frame pointer when one is needed.
In line with GCC Internals info on FIXED_REGISTERS ("except on machines
where that can be used as a general register when no frame pointer is
needed") I have no
I'm porting gcc 4.6.2 to a 16 bit CPU that has four GP registers. I've
chosen to allocate R3 as the frame pointer when one is needed.
In line with GCC Internals info on FIXED_REGISTERS ("except on machines
where that can be used as a general register when no frame pointer is
needed") I have no
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