Hello,
I am working with c6x processor from TI. It has a VLIW architecture.
It has 32 registers namedly a0-a15 and b0-b15. b15 is used as the SP
in the current port.
I am facing a problem with the scheduler of GCC.
Following is the c code I was compiling -
***
int mul
Hello,
I am working with c6x processor from TI. It has a VLIW architecture.
It has 32 registers namedly a0-a15 and b0-b15. b15 is used as the SP
in the current port.
I am facing a problem with the scheduler of GCC.
Following is the c code I was compiling -
***
int mult
Hello,
I am working with a VLIW processor and GCC-4.0-20040911. There is a
problem in the dependency calculation of GCC. GCC is giving
write-after-read a higher priority than write-after-write. Thus, as in
the following code, GCC gives a write-after-read dependency between
the 2 instructions. Due t
Hello,
I have attached the dump after the scheduler. The branch instruction
is a conditionally executed branch instruction. So it is represented
as RTL COND_EXEC.
Regards,
Kunal
On Tue, 08 Mar 2005 10:14:05 -0500, Vladimir Makarov
<[EMAIL PROTECTED]> wrote:
> Kunal Parmar wrote:
>
Hello,
Thanks alot Vladimir and Daniel.
Regards,
Kunal
On Tue, 8 Mar 2005 11:12:46 -0500, Daniel Jacobowitz <[EMAIL PROTECTED]> wrote:
> On Tue, Mar 08, 2005 at 09:38:19PM +0530, Kunal Parmar wrote:
> > Hello,
> > I have attached the dump after the scheduler. The branch
Hi,
I am working on porting GCC to a new RISC architecture. The ISA does not
have a "Jump and Link Register" instruction. So I am simulating one by
replacing
jal [reg]
by
load ra, Lret
jr reg
Lret:
in RTL.
But my return label is getting optimized away. Could you ple
Hi,
>> I am working on porting GCC to a new RISC architecture. The ISA does
>> not have a "Jump and Link Register" instruction. So I am simulating
>> one by replacing
>> jal [reg]
>> by
>> load ra, Lret
>> jr reg
>> Lret:
>>
>> in RTL.
>> But my return label is getting
Hi Jim,
>>> But my return label is getting optimized away. Could you please tell
>>> me how to avoid this.
>
>You may also need to add a (USE (REG RA)) to the call pattern. Gcc
will see that you set a register to the value of the
>return label, but it won't see any code that uses that register,
Hi Joern,
>The insn that loads the return register with the label needs a REG_LABEL
>note to avoid the ref count dropping to zero.
The insn has a REG_LABEL (foo.c.110r.vregs) and the label also has a ref
count of 1.
>You would have to put a (set (pc) (reg RA)) into the pattern of the
>call in
Hi all,
I am porting GCC to a new 16 bit RISC architecture which does not have
multiplication and division instructions. I figured that I have to provide
emulation routines for the multiplication and division which will be
inserted into libgcc2.a. But I am confused about which versions of these
r
Hi Ian,
On Tue, Apr 22, 2008 at 1:24 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> It depends on UNITS_PER_WORD. If UNITS_PER_WORD is 4, you need
> __mulsi3. If UNITS_PER_WORD is 2, you need __mulhi3, and, if you have
> 32-bit integer types, you will also need __mulsi3. In the latter cas
Hi Ian,
> Yes, I think __mulsi3 will be built for you automatically.
I gave a definition of __mulhi3 for my architecture. But I don't get
__mulsi3 in libgcc.a. Do I have to enable some options for this ?
Thanks in advance,
Kunal Parmar
Hi Ian,
On Tue, Apr 22, 2008 at 7:12 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> Looking at libgcc2.h, it seems like you might need to define
> LIBGCC2_UNITS_PER_WORD in your tm.h file.
That solved my problem. Thanks a ton !
Kunal
Hi,
I wanted support for software floating point on the architecture. I am
using fp-bit.c & dp-bit.c and have defined FLOAT_TYPE_SIZE as 32 and
DOUBLE_TYPE_SIZE as 64. dp-bit.c requires __muldi3. How do I enable
emulation of 64 bit multiply in libgcc2.a ?
Thanks in advance,
Kunal Parmar
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