Steven Bosscher wrote:
All of this feels (to me anyway) like adding a lot of code to the
middle end to support MEP specific arch features. I understand it is
in the mission statement that more ports is a goal for GCC, but I
wonder if this set of changes is worth the maintenance burden...
FWIW,
Steven Bosscher wrote:
On 3/28/07, Julian Brown <[EMAIL PROTECTED]> wrote:
Steven Bosscher wrote:
> All of this feels (to me anyway) like adding a lot of code to the
> middle end to support MEP specific arch features. I understand it is
> in the mission statement that more port
actice with a little linker magic. It wasn't really production-quality
code though, I admit.
Perhaps the indirection table can safely hold only those functions whose
address is taken? (Or maybe that was assumed anyway?)
Julian
--
Julian Brown
CodeSourcery, LLC
On 2005-04-10, Mark Mitchell <[EMAIL PROTECTED]> wrote:
>
> * The DejaGNU testsuite has been run, and compared with a run of
> the testsuite on the previous release of GCC, and no regressions are
> observed.
>
> If you are willing to help, please download the release candidate, build
> it o
On 2005-04-11, Julian Brown <[EMAIL PROTECTED]> wrote:
> On 2005-04-10, Mark Mitchell <[EMAIL PROTECTED]> wrote:
>>
>> * The DejaGNU testsuite has been run, and compared with a run of
>> the testsuite on the previous release of GCC, and no regressions a
On 2005-04-18, Mark Mitchell <[EMAIL PROTECTED]> wrote:
>
> RC2 is available here:
>
> ftp://gcc.gnu.org/pub/gcc/prerelease-4.0.0-20050417/
>
> As before, I'd very much appreciate it if people would test these bits
> on primary and secondary platforms, post test results with the
> contrib/test_su
On Mon, 24 Feb 2020 15:03:21 +0300 (MSK)
Alexander Monakov wrote:
> On Mon, 24 Feb 2020, Andreas Schwab wrote:
>
> > On Feb 24 2020, Petr Tesarik wrote:
> >
> > > On Mon, 24 Feb 2020 12:29:40 +0100
> > > Andreas Schwab wrote:
> > >
> > >> On Feb 24 2020, Petr Tesarik wrote:
> > >>
> > >
On Fri, 28 Aug 2015 17:50:53 +
Joseph Myers wrote:
> shinwell = Mark Shinwell
> (Jane Street)
Mark's current address is mshinw...@janestreet.com.
Julian
On Mon, 11 Jan 2016 13:51:25 -0700
Tom Tromey wrote:
> > "Michael" == Michael Matz writes:
>
> Michael> Well, that's a hack. A solution is to design something that
> Michael> works generally for garbage collected languages with such
> Michael> requirements instead of arbitrarily limiting
On Mon, 1 Sep 2014 09:14:31 +0800
Peng Fan wrote:
> On 09/01/2014 08:09 AM, Matt Thomas wrote:
> >
> > On Aug 31, 2014, at 11:32 AM, Joel Sherrill
> > wrote:
> >> I think this is totally expected. You were passed a u8 pointer
> >> which is aligned for that type (no restrictions likely). You cas
On Wed, 9 Oct 2019 14:40:42 +0100
Jozef Lawrynowicz wrote:
> Constants generated for modes with fewer bits than in HOST_WIDE_INT
> must be sign extended to full width (e.g., with gen_int_mode). For
> constants for modes with more bits than in HOST_WIDE_INT the implied
> high order bits of that co
On Wed, 05 Oct 2011 10:37:22 +0900
shiot...@rd.ten.fujitsu.com (塩谷晶彦) wrote:
> Hi, Maintainer,
>
> I found some incidents in
> http://gcc.gnu.org/onlinedocs/gcc/ARM-NEON-Intrinsics.html#ARM-NEON-Intrinsics
>
> Please check the following:
>
> |6.54.3.8 Comparison (less-than-or-equal-to)
> |
> |
On Mon, 11 Jan 2010 09:52:59 +
Ramana Radhakrishnan wrote:
> cam-bc3-b12:ramrad01 68 > ocamlc -c neon-schedgen.ml
> File "neon-schedgen.ml", line 51, characters 0-10:
> Unbound module Utils
>
> It sounds like a configuration issue but given my rather rusty ocaml
> skills - I'm not sure wher
On Thu, 26 Feb 2009 15:54:14 +
Andrew Haley wrote:
> Paul Brook wrote:
> >> Well, but wouldn't it still be nice if
> >> __builtin_return_address(N) was implemented for N>0 by libcalling
> >> into the unwinder for you? Obviously this would still have to
> >> return NULL at runtime when you'
On Fri, 27 Feb 2009 13:32:11 +
Julian Brown wrote:
> GLIBC already knows how to do backtracing if the ARM-specific unwind
> tables are present (.ARM.exidx, etc.), using _Unwind_Backtrace.
I'm told this probably isn't true for upstream GLIBC -- but we
definitely have a pa
On Wed, 3 Jun 2009 21:39:34 +1200
Michael Hope wrote:
> How does the combine stage work? It looks like it could get multiple
> potential matches for a set of RTLs. Does it use some type of costing
> function to pick between them? Can I tell combine that a umulhisi3 is
> cheaper than a mulsi3?
On Mon, 02 May 2022 19:10:41 -0700
Andras Tantos wrote:
> To a previous problem I've asked, Andrew Pinski replied that I should
> merge all *movsi patterns into a single one to avoid (in that case)
> strange deletions in the generated assembly. Is that possible here? It
> appears to me that I wou
On Wed, 22 Mar 2023 18:27:28 -0400
Sid Maxwell via Gcc wrote:
> Is there anyone on the list with experience with the gcc 4.3
> codebase? I'm currently maintaining a fork of it, with a PDP10 code
> generator.
>
> I've run into an issue involving the transformation of a movmemhi to a
> single PDP
On Mon, 10 Mar 2014 15:27:06 +0100
Shahbaz Youssefi wrote:
> Feedback
>
>
> Please let me know what you think. In particular, what would be the
> limitations of such a syntax? Would you be interested in seeing this
> extension to the GNU C language? What alternative symbols do you think
On Fri, 14 Mar 2014 12:52:35 +0100
David Guillen wrote:
> If I allow also a 'PLUS' expression to be a valid address (adding the
> restriction that the two addends are a register and a constant) it
> happens (sometimes) that gcc comes up with an expression like this
> one:
>
> (plus:SI (plus
On Thu, 27 Mar 2014 09:41:28 -0600
Jeff Law wrote:
> On 03/27/14 07:50, Felix Yang wrote:
> > Hello,
> >
> > I find DCE in sched2 is disabled for C6X backend. Is this a
> > performance consideration? Or a GCC BUG?
> > And under what situations should we disable DCE in sched2?
> > C
On Thu, 27 Mar 2014 16:02:49 +
Julian Brown wrote:
> On Thu, 27 Mar 2014 09:41:28 -0600
> Jeff Law wrote:
>
> > On 03/27/14 07:50, Felix Yang wrote:
> > > Hello,
> > >
> > > I find DCE in sched2 is disabled for C6X backend. Is this a
>
On Fri, 27 Jun 2008 15:52:22 +0530
"Mohamed Shafi" <[EMAIL PROTECTED]> wrote:
> If the condition in the 'if' instruction is satisfied the processor
> will execute the next instruction or it will replace with a nop. So
> this means that i can instructions similar to:
>
> if eq Rx, Ry
> add Rx, R
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