Re: Vector registers on MIPS arch

2016-04-18 10:33 GMT+01:00 Richard Biener : > On Mon, Apr 11, 2016 at 1:54 PM, Ilya Enkovich wrote: >> 2016-04-10 3:34 GMT+03:00 David Guillen Fandos : >>> On 07/04/16 09:09, Ilya Enkovich wrote: >>>> 2016-04-07 0:49 GMT+03:00 David Guillen Fandos : >>>&g

Re: libgcc_s_sjlj-1 and libstdc++-6 dependency...

You are probably looking for: -static-libgcc -static-libstdc++ Cheers, David 2015-02-04 18:06 GMT+00:00 Umesh Kalappa : > Hi All, > > Was configured and build gcc 4.8.3 for windows on linux using mingw . > > configure options as > > ../../src45x/gcc/configure --build=i686-pc-linux-gnu --host=i68

Legitimize address after reload

Hello, I'm writing a simple gcc backend and I'm experiencing a weird thing regarding address legitimation process. Two scenarios: If I only allow addresses to be either a register or symbols my gcc works. To do so I add the restrictions into the TARGET_LEGITIMATE_ADDRESS_P macro. This makes gcc t

Re: Legitimize address after reload

regsiters themselves. This is because any reg is OK for base reg. I'm pretty sure I'm behaving similarly to arm, cris or x86 backends. Thanks, David 2014-03-14 13:11 GMT+01:00 Julian Brown : > On Fri, 14 Mar 2014 12:52:35 +0100 > David Guillen wrote: > >> If I allow als

Re: Legitimize address after reload

the address to be in a register. Any ideas? And, anyone can give me a hint on how to debug this issues? I'd like to discover where in the gcc source this memory RTX expression is created and why it is not expanded to be a valid address. Thanks a lot! David 2014-03-14 18:56 GMT+01:00 DJ Del

Re: Legitimize address after reload

Yep thanks, As you guys pointed the problem was the improper handling of the strict_p parameter. Thanks! 2014-03-18 20:13 GMT+01:00 Richard Sandiford : > Richard Sandiford writes: >> What DJ meant below was that you should reject all pseudo registers >> if strict_p. I.e. REG_P (foo) should be:

Spill registers not available

Hello! As I stated on other emails I'm writing a backend. I'm facing a problem regarding register modes. The thing is: I don't know how to handle non-SI modes. I've read many backends for different arches but I don't really get it, sorry. In my case I've started with a x86 backend. This arch has

collect2 "-o" argument position problem

Hello guys, I don't know whether this is the best place to ask for this, but anyway, here we go: I have two different commandlines for collect2 (I got them after using -v in gcc) and I found out that the original one does not work because of the position in the parameter list. Error: /home/davi

Re: collect2 "-o" argument position problem

ER "/lib/ld-linux.so.2" #define GNU_USER_DYNAMIC_LINKER GLIBC_DYNAMIC_LINKE #define SUBTARGET_EXTRA_SPECS \ { "link_emulation", GNU_USER_LINK_EMULATION },\ { "dynamic_linker", GNU_USER_DYNAMIC_LINKER } Any ideas? Thank you! 2014-04-03 1:17 GMT+02:00 Jonathan Wak

Re: gcc build second pass : C compiler cannot create executables

Can you check whether crt1.o and crt1.o exist? And the path where they do live. Also it would be interesting to know the exact commandline (check config.log). 2014-04-08 14:13 GMT+02:00 Mo Jia : > Try to make a gcc cross compiler , > > 0 perpare vars in env > > export HOST=x86_64-pc-linux

Re: Performance gain through dereferencing?

Hello, I completely agree with David. Note that your results will greatly vary depending on the machine you run the tests on. Performance on such tests it is very machine-dependant, so the conclusion cannot be generalized. David 2014-04-16 16:49 GMT+02:00 David Brown : > > Hi, > > You cannot lea

Vector registers on MIPS arch

Hello there! I'm trying to add some vector registers to a MIPS arch (32 bit). This arch has 32 x 128 bit registers that can essentially be seen as V4SF. So far I'm using this test: volatile float foo __attribute__ ((vector_size (16))); volatile float bar __attribute__ ((vector_size (16))); int m

Re: Vector registers on MIPS arch

On 04/04/16 10:55, Ilya Enkovich wrote: > 2016-04-02 3:32 GMT+03:00 David Guillen Fandos : >> Hello there! >> >> I'm trying to add some vector registers to a MIPS arch (32 bit). This >> arch has 32 x 128 bit registers that can essentially be seen as V4S

Re: Vector registers on MIPS arch

On 05/04/16 09:13, Ilya Enkovich wrote: > 2016-04-05 1:59 GMT+03:00 David Guillen Fandos : >> >> >> On 04/04/16 10:55, Ilya Enkovich wrote: >>> 2016-04-02 3:32 GMT+03:00 David Guillen Fandos : >>>> Hello there! >>>> >>>> I&#

Re: Vector registers on MIPS arch

On 06/04/16 10:44, Ilya Enkovich wrote: > 2016-04-06 1:50 GMT+03:00 David Guillen Fandos : >> >> Thanks again Ilya, >> >> That seems to help to solve the problem. Now I'm facing another issue. >> It seems the tree-vec-generic pass is promoting my vector oper

Re: Vector registers on MIPS arch

On 07/04/16 09:09, Ilya Enkovich wrote: > 2016-04-07 0:49 GMT+03:00 David Guillen Fandos : >> >> Thanks a lot Ilya! >> >> I managed to get it working. There were some bugs regarding register >> allocation that ended up promoting the class to be BLKmode instead of

GCC 4.9 generates bigger code for x86

Hi all, I just noticed that 4.9 generates some code overhead for 386 machines respect to 4.8. In my test case I used 4.8.1 and 4.9.1 and realized that when compiling with "-Os -fno-exceptions -fno-align-functions -fomit-frame-pointer" certain things change: On 4.9 the backend adds some "nop"

Weird optimization for tuples?

Hello! I have the following function std::tuple getRawIdx(uint16_t tidx) { return std::make_tuple(localidx.entries[tidx].indx_ptr, localidx.entries[tidx].indx_size); } Where s is a struct like typedef struct __attribute__((packed)) { uint32_t indx_ptr; uint8_t indx_size; } _i_