t penalty to
about
2x that of a 3AC machine. If you think about this for a while, the
reason
will become readily apparent.
In order to reach this 2x figure, it requires a good understanding of
how
the data flows through the accumulator in an accumulator arch.
Toshi
Alan Lehotsky - [EMAIL PROTECTED]
Carbon Design Systems, Inc
FYI for the application my company is developing (integer and bit-field
intensive with very little floating point),
we have found gcc to be 10-30% FASTER than icc8.0.
We were told that this was partially because icc doesn't optimize unsigned
expressions very well
(I'm dubious that this is the ca
On Jul 17, 2005, at 19:15, Stefan wrote:
I have some problems with using inline PowerPC assembly in GCC
(4.0.1). Consider the following code:
void save_fp_register(double* buffer)
{
asm("stfd F0, 0(%0)" : : "r" (buffer) );
}
Try using 'b' for the constraint - that selects fo
immediate mode.)
The (define_insn_and_split “movdf” …) is conditioned on “reload_completed”.
Is there some other trick I need get the constant hoisted. I have already set
the rtx cost of the CONST_DOUBLE ridiculously high (like 10 insns)
Alan Lehotsky
https://codegentllc.com
On Jun 25, 2020, at 6:37 PM, Jeff Law mailto:l...@redhat.com>>
wrote:
On Thu, 2020-06-25 at 15:46 -0400, Alan Lehotsky wrote:
I’m working on a GCC 8.3 port to a load/store architecture with a 32-bit
data-path between registers and memory;
looking at the gcc.dg/loop-9.c test, I fail t
I’m in the process of upgrading a gcc port, but my client is using a gcc 4.4.1
port right now and has run into a scheduler bug. This seems to have been fixed
at some point, as the 8.3.1 code base doesn’t seem to have the bug. But they’d
like a fix on their 4.4.1 base.
Basically, what I see is
there a bigger hammer I’m missing?
Alan Lehotsky
https://codegentllc.com
I’m doing some final polishing on a gcc 8.3 upgrade and taking a look at the
unsupported tests. Most of them are completely sensible (my port doesn’t
support trampolines, for example). But gcc.c-torture/execute/pr78622.c is
marked as unsupported. That appears to be due to the line
{ dg-r
I have a funny situation where I’m trying to build a cross compiler for x86
hosted on x86 where I’d like to use the native headers and libraries.
I tried defining INCLUDE_DEFAULTS, and that didn’t help. The documentation
says it’s ignored for cross compilers.
Any suggestions, or am I going to
I have a tool chain for an experimental processor, built starting with release
or snapshot distributions of
binutils-2.21
cgen-20110901
gcc-4.6.1
newlib-1.19.0
gdb 7.2
I'm using SVN for version control locally.
I'd like to upgrade it to a newer source bas
I’m trying to grapple with connecting dejagnu to a QEMU simulator; not finding
any obvious examples to work with.
I’ve had a lot of familiarity using CGEN simulators connected to dejagnu, but
QEMU’s a new breed of cat….
Can anyone point me to a boards/.exp that is based on using QEMU, or
provi
While I really like machine-readable (and searchable) text online for the GCC
internals, there's still an atavistic streak in me that wants hard copy that I
can put post-it notes on, run a highlighter over relevant passages or read when
I'm not near a computer screen.
I have two bound hard-copi
I'm working on a port to a Harvard architecture where the data memory addresses
are only 14 bits wide (e.g. 16kb) and the instruction address space is 21 bits
wide.
I do not want to define Pmode as PSImode; the machine has separate address
registers for data memory AND with such limited data m
Almost certainly you will run into severe problems in the reload phase.
You might also profitably study the ip2k port. This is a ALU machine, but it
does have multiple
address registers.
-Original Message-
>From: redriver jiang
>Sent: Mar 17, 2010 8:55 AM
>To: gcc@gcc.gnu.org
>Subject
This is normal unix behavior (unless you have some kind of shell that I'm
unfamiliar with.)
When you use & to create a subjob, it is still attached to your terminal
session.
Take a look at the at(1) or batch(1) commands if you really want to execute a
command and logout while it's still runnin
Look at the implementation of the IP2K compiler and linker.
It uses a segmented paged architecture just like the machine you are
describing.
In essence what we did was implement linker relaxation to deal with
this.
When we called any function, we emitted the appropriate long-call by
settin
I've built a generic 4.1.0 for RH7.3 x86 linux (I did a make bootstrap)
Compiling a rather large file, I get
tmp.f_00.cxx:26432: error: unrecognizable insn:
(insn 173 172 174 9 (set (reg:QI 122)
(const_int 128 [0x80])) -1 (nil)
(nil))
tmp.f_00.cxx:26432: internal compiler err
I participated in a port to an 8-bit internet toaster 4 years ago (the Ubicom
IP2k chip).
It's distributed as part of the gcc-3.x releases, but has been dropped from the
gcc-4.x distributions.
The IP2k was a very restrictive environment, and it took a lot of work to get
it to generate really t
Again, the GCC3 distribution has a port of the IP2K microcontroller.
It has a hardware call stack, but the data stack is implemented
entirely in software.
You will have to dedicate a register to act as the data-stack
pointer. I suppose if you limit yourself to
writing functions with NO sta
On Apr 11, 2006, at 03:46, Colm O' Flaherty wrote:
I'm not quite sure I follow you.. if its possible to dedicate a
register to act as the data-stack pointer, and implement it that
way, why would I want to "keep the SP as a virtual register"? I'm
not being antagonistic when I say that.. I'
I have a gcc 4.6.1 port that has the same sort of problems. I tried
selectively porting some patches from later 4.6 releases, but they didn't seem
to actually address the issue. I haven't looked at the trunk to see if there
are patches that are more apropos.
On Oct 10, 2013, at 12:33 PM, Jef
When a peephole is recognized, the first insn in the group is replaced by a
pseudo insn that contains all the referenced operands in the TEMPLATE and sets
an INSN_CODE to indicate which peephole matched.
This is all well and good, except that if the peephole involves a CALL_INSN,
final_scan_ins
I'm certain there are better ways; can you be more specific though?
Or are you just talking about defining a sibcall_epilogue pattern?
On Jul 8, 2012, at 5:26 PM, Andrew Pinski wrote:
> On Sun, Jul 8, 2012 at 2:23 PM, Alan Lehotsky wrote:
>> When a peephole is recognized, the fir
I'm looking at code generated for a new port of gcc using 4.6.1 and failing
execute/950607-2.c with -O0 only
The target chip has only 32 bit instructions, so it's using
do_jump_by_parts__rtx() to expand the compare.
I've set up my .md to use the CCmode.
I see one case that seems really stupid
So, I found the patch to do_jump_by_parts_greater_rtx() by Eric Botcazou that
should address the stupid code and the redundant branch.
Should have done a broader search before I wasted email bandwidth...
On Oct 31, 2012, at 1:51 PM, Alan Lehotsky wrote:
> I'm looking at code generat
The V constraint is essentially implemented by checking that the addressing
mode presented is NOT offsettable. But that's done by adding
GET_MODE_SIZE(mode) - 1.
I've got a machine that supports indirection but not offsetting or indexing.
But the V constraint fails for any
(mem:QI (
I'm obvkously doing something stupid here; but I'm at a loss to figure it out.
Porting to a machine where most instructions set some condition codes and
before hoisting, we have
(insn 1205 1204 1206 65 (set (reg:CC_ZN 24 *cc)
(compare:CC_ZN (reg:SI 843)
(reg:SI 844)))
../..
I'm looking at a machine with limited stack, and no push instructions or
displaced-addressing mode. The call instruction stores the return address in
the link register.
For non-recursive functions we save the return address in a static memory
location, but I can't find a way to tell the DWARF2
Am I correct in my understanding that you can't put a branch instruction in the
delay slot of a branch instruction?
Semantically, the HW I'm looking at annuls the branch in the delay slot if the
first branch is taken, but any other instructions are not annulled; but it
appears that there's no w
I'm using the CCmode model for condition-code handling in a 4.6.1 based
compiler. Every other port I've done used the CC0 model, so I'm probably doing
something misguided here.
I'm down to just 170 failures in the check-gcc testsuites, so it's looking
pretty solid; of the failures about 30 are
Martin,
I did a port of GCC to the Analog Devices SHARC chip. I ended up
supporting 3 kinds of pointers for this chip (two for address
spaces and one for byte pointers - the chip itself is only word
addressable (although words can be from 16 to 48 bits in size
depending on what memory is
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