On Wed, Jun 24, 2020 at 9:05 PM Gary Oblock via Gcc wrote:
>
> Richard,
>
> First off I did suspect INDIRECT_REF wasn't supported, thanks for
> confirming that.
>
> I tried what you said in the original code before I posted
> but I suspect how I went at it is the problem. I'm probably
> doing some
Hello,
I am working on a basic block coverage counter which
mimics -fsanitize-coverage=trace-pc but has more features. My problem is
that when instrumenting multiple C files (e.g., test1.c test2.c test3.c), I
want to generate correspondingly three coverage logs (test1.log, test2.log,
test3.log), s
David Edelsohn writes:
> Hi, Gaius
>
> Thanks for your diligent effort to complete this port of Modula-2 and
> prepare it for inclusion in GCC. I have forwarded the proposal to the
> GCC Steering Committee.
>
> Thanks, David
Hi David,
many thanks for forwarding the proposal - always great fun
Hi
RTEMS supports over 15 processor architectures and we would like to ensure
that TLS is supported on all rather than just a handful of popular ones
(arm, x86, powerpc, sparc, etc). I know of Ulrich Drepper's document (
https://www.akkadia.org/drepper/tls.pdf) but it is a few years old and
cover
I’m working on a GCC 8.3 port to a load/store architecture with a 32-bit
data-path between registers and memory;
looking at the gcc.dg/loop-9.c test, I fail to pass because I have split the
move of a double constant to memory into multiple moves (4 in fact, because I
only have a 16-bit immedi
On 6/25/20 2:34 PM, Joel Sherrill wrote:
Hi
RTEMS supports over 15 processor architectures and we would like to ensure
that TLS is supported on all rather than just a handful of popular ones
(arm, x86, powerpc, sparc, etc). I know of Ulrich Drepper's document (
https://www.akkadia.org/drepper/t
On Thu, Jun 25, 2020 at 2:54 PM Nathan Sidwell wrote:
> On 6/25/20 2:34 PM, Joel Sherrill wrote:
> > Hi
> >
> > RTEMS supports over 15 processor architectures and we would like to
> ensure
> > that TLS is supported on all rather than just a handful of popular ones
> > (arm, x86, powerpc, sparc,
On Thu, Jun 25, 2020 at 1:34 PM Joel Sherrill wrote:
>
> On Thu, Jun 25, 2020 at 2:54 PM Nathan Sidwell wrote:
>
> > On 6/25/20 2:34 PM, Joel Sherrill wrote:
> > > Hi
> > >
> > > RTEMS supports over 15 processor architectures and we would like to
> > ensure
> > > that TLS is supported on all rat
Snapshot gcc-8-20200625 is now available on
https://gcc.gnu.org/pub/gcc/snapshots/8-20200625/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 8 git branch
with the following options: git://gcc.gnu.org/git/gcc.git branch
On Thu, 2020-06-25 at 15:46 -0400, Alan Lehotsky wrote:
> I’m working on a GCC 8.3 port to a load/store architecture with a 32-bit
> data-path between registers and memory;
>
> looking at the gcc.dg/loop-9.c test, I fail to pass because I have split the
> move of a double constant to memory in
On Jun 25, 2020, at 6:37 PM, Jeff Law mailto:l...@redhat.com>>
wrote:
On Thu, 2020-06-25 at 15:46 -0400, Alan Lehotsky wrote:
I’m working on a GCC 8.3 port to a load/store architecture with a 32-bit
data-path between registers and memory;
looking at the gcc.dg/loop-9.c test, I fail to pass beca
On June 26, 2020 3:24:24 AM GMT+02:00, Alan Lehotsky wrote:
>On Jun 25, 2020, at 6:37 PM, Jeff Law
>mailto:l...@redhat.com>> wrote:
>
>On Thu, 2020-06-25 at 15:46 -0400, Alan Lehotsky wrote:
>I’m working on a GCC 8.3 port to a load/store architecture with a
>32-bit data-path between registers and
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