On Fri, Aug 18, 2017 at 10:29:04AM +1200, Michael Clark wrote:
> Sorry I had to send again as my Apple mailer is munging emails. I’ve disabled
> RTF.
>
>
> This one is quite interesting:
>
> - https://cx.rv8.io/g/WXWMTG
>
> It’s another target independent bug. x86 is using some LEA followed by
> On 18 Aug 2017, at 10:41 PM, Gabriel Paubert wrote:
>
> On Fri, Aug 18, 2017 at 10:29:04AM +1200, Michael Clark wrote:
>> Sorry I had to send again as my Apple mailer is munging emails. I’ve
>> disabled RTF.
>>
>>
>> This one is quite interesting:
>>
>> - https://cx.rv8.io/g/WXWMTG
>>
>>
> On 18 Aug 2017, at 10:56 PM, Michael Clark wrote:
>
>>
>> On 18 Aug 2017, at 10:41 PM, Gabriel Paubert wrote:
>>
>> On Fri, Aug 18, 2017 at 10:29:04AM +1200, Michael Clark wrote:
>>> Sorry I had to send again as my Apple mailer is munging emails. I’ve
>>> disabled RTF.
>>>
>>>
>>> This o
On Fri, Aug 18, 2017 at 10:56:10PM +1200, Michael Clark wrote:
>
> > On 18 Aug 2017, at 10:41 PM, Gabriel Paubert wrote:
> >
> > On Fri, Aug 18, 2017 at 10:29:04AM +1200, Michael Clark wrote:
> >> Sorry I had to send again as my Apple mailer is munging emails. I’ve
> >> disabled RTF.
> >>
> >>
On Fri, 2017-08-18 at 10:29 +1200, Michael Clark wrote:
>
> This one is quite interesting:
>
> - https://cx.rv8.io/g/WXWMTG
>
> It’s another target independent bug. x86 is using some LEA followed
> by SAR trick with a 3 bit shift. Surely SHL 27, SAR 27 would suffice.
> In any case RISC-V seems l
On 8/14/17, Alan Modra wrote:
> On Sun, Aug 13, 2017 at 10:25:14PM +0930, Alan Modra wrote:
>> On Sun, Aug 13, 2017 at 03:35:15AM -0700, David Wohlferd wrote:
>> > Using "m"(*pStr) as an (unused) input parameter has no effect.
>>
>> Use "m" (*(const void *)pStr) and ignore the warning, or use
>> "
On 08/17/2017 03:29 PM, Michael Clark wrote:
> hand coded x86 asm (no worse because the sar depends on the lea)
>
> sx5(int):
> shl edi, 27
> sar edi, 27
> movsx eax, dl
Typo in the register, but I know what you mean. More interestingly, edi
already has the sign-ext
On Fri, Aug 18, 2017 at 1:09 AM, Freddie Chopin wrote:
> On Thu, 2017-08-17 at 22:27 -0500, R0b0t1 wrote:
>> On Thu, Aug 17, 2017 at 4:44 PM, R0b0t1 wrote:
>> > When compiling libssp, ssp.c, function __guard_setup:
>> > O_RDONLY is undeclared (ssp.c:93:34),
>> > ssize_t is an unknown type name (s
On Fri, 2017-08-18 at 11:17 -0500, R0b0t1 wrote:
> Just to check, this is actually an
> arm-none-eabi toolchain? I looked over the compilation flags and it
> looks like it supports all Cortex-M processor features like such a
> toolchain should. Most instructions I could find seemed to build a
> mor
Hi,
My first question would be why are you using the ChangeLog files at all?
It seems like it would be a lot more straight forward to just look at
blame for the thing that changed.
thanks
Trev
On Fri, Aug 18, 2017 at 09:32:34AM +0800, Leslie Zhai wrote:
>
>
> 在 2017年08月17日 23:10, David Malcol
R0b0t1 kirjoitti 18.8.2017 klo 19:17:
On Fri, Aug 18, 2017 at 1:09 AM, Freddie Chopin wrote:
On Thu, 2017-08-17 at 22:27 -0500, R0b0t1 wrote:
On Thu, Aug 17, 2017 at 4:44 PM, R0b0t1 wrote:
When compiling libssp, ssp.c, function __guard_setup:
O_RDONLY is undeclared (ssp.c:93:34),
ssize_t is
On Thu, Aug 17, 2017 at 05:22:34PM +, paul.kon...@dell.com wrote:
> I think G-J said "... LRA focusses just comfortable, orthogonal targets"
> which is not quite the same thing.
>
> I'm a bit curious about that, since x86 is hardly "comfortable orthogonal".
> But if LRA is targeted only at
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