On Monday 06 July 2015 12:04 PM, Richard Biener wrote:
>> The point being ARC ISA provides a neat feature where core only considers
>> lower 5
>> > bits of bitpos operands. Thus we can make such behaviour not only
>> > deterministic in
>> > the context of ARC, but also optimal, eliding the need f
Hi,
Many of the floating point-related builtins are type-generic, including
__builtin_{isfinite,isinf_sign,isinf,isnan,isnormal,isgreater,islesser,isunordered}.
However, __builtin_signbit is not. It would make life easier for the
implementation of IEEE in Fortran if it were, and probably for so
On Mon, Jul 6, 2015 at 11:49 AM, FX wrote:
> Many of the floating point-related builtins are type-generic, including
> __builtin_{isfinite,isinf_sign,isinf,isnan,isnormal,isgreater,islesser,isunordered}.
> However, __builtin_signbit is not. It would make life easier for the
> implementation of
> Please look at builtins.def, grep for TYPEGENERIC.
Sure, I can define it as TYPEGENERIC in the builtins.def, like this:
Index: builtins.def
===
--- builtins.def(revision 225434)
+++ builtins.def(working copy)
@@ -48
Hello,
The attached reproducer[1] seems to trigger a code generation issue at
least on x86_64-linux:
$ gnatmake -q p -O3 -gnatn
$ ./p
raised PROGRAM_ERROR : p.adb:9 explicit raise
The bottom line is that when Success is False in Q.Get (q.adb, around
line 40) its value is clobber
On 07/05/2015 05:11 AM, Ajit Kumar Agarwal wrote:
All:
I am wondering allocation of hot data structure closer to the top of
the stack increases the performance of the application. The data
structure are identified as hot and cold data structure and all the
data structures are sorted in decreasin
On 07/01/2015 10:14 PM, DJ Delorie wrote:
In this bit of code in explow.c:
/* By passing constant addresses through registers
we get a chance to cse them. */
if (! cse_not_expected && CONSTANT_P (x) && CONSTANT_ADDRESS_P (x))
x = force_reg (address_mode, x);
On the rl78 it res
Given a test case like this:
typedef struct {
unsigned char no0 :1;
unsigned char no1 :1;
unsigned char no2 :1;
unsigned char no3 :1;
unsigned char no4 :1;
unsigned char no5 :1;
unsigned char no6 :1;
unsigned char no7 :1;
} __BITS8;
#define
On Mon, Jul 06, 2015 at 04:45:35PM -0400, DJ Delorie wrote:
> Combine gets as far as this:
>
> Trying 5 -> 9:
> Failed to match this instruction:
> (parallel [
> (set (mem/v/j:QI (const_int 240 [0xf0]) [0 MEM[(volatile union
> un_per0 *)240B].BIT.no4+0 S1 A16])
> (ior:QI (mem/
Hello,
Does GCC generate LDRD/STRD (Register) forms [A8.8.74/A8.8.211 per ARMv7-A
& ARMv7-R ARM]?
Based on various attempts to write code to get GCC to generate a sample
form, and subsequently inspecting the code I see in
config/arm/arm.c/output_move_double () & arm.md [GCC 4.9.2], I think that
t
On Tue, Jul 7, 2015 at 10:05 AM, Anmol Paralkar (anmparal)
wrote:
> Hello,
>
> Does GCC generate LDRD/STRD (Register) forms [A8.8.74/A8.8.211 per ARMv7-A
> & ARMv7-R ARM]?
>
> Based on various attempts to write code to get GCC to generate a sample
> form, and subsequently inspecting the code I see
> Did you try just a define_split instead? Ugly, but it should work I think.
It doesn't seem to be able to match a define_split :-(
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