Hi,
I have a case which will generate abs instructions.
int main(int argc)
{
if (argc < 0)
argc = -(unsigned int)argc;
return argc;
}
To my understanding, given that argc=0x8000 in 32bit int plaform,
the result of (unsigned int)argc is well defined and should be 0x8000
On 06/28/2013 08:53 AM, Shiva Chen wrote:
> I have a case which will generate abs instructions.
>
> int main(int argc)
> {
> if (argc < 0)
>argc = -(unsigned int)argc;
> return argc;
> }
>
> To my understanding, given that argc=0x8000 in 32bit int plaform,
> the result of
On 06/28/2013 11:11 AM, Andrew Haley wrote:
On 06/28/2013 08:53 AM, Shiva Chen wrote:
I have a case which will generate abs instructions.
int main(int argc)
{
if (argc < 0)
argc = -(unsigned int)argc;
return argc;
}
To my understanding, given that argc=0x8000 in 32b
On Fri, 28 Jun 2013, Andrew Haley wrote:
On 06/28/2013 08:53 AM, Shiva Chen wrote:
I have a case which will generate abs instructions.
int main(int argc)
{
if (argc < 0)
argc = -(unsigned int)argc;
return argc;
}
To my understanding, given that argc=0x8000 in 32bit int
Hi, I have a question about register renaming in rtl loop unroll.
For an example loop:
.L1:
[r162] <- x
r162 <- r162 + 4
...
b .L1
After unrolling:
.L1:
[r162] <- x
r197 <- r162 + 4
r162 <- r197
...
[r162] <- y
r162 <- r197 + 4
...
b .L1
Why not:
.L1:
[r162] <- x
r16
> Hi, I have a question about register renaming in rtl loop unroll.
> For an example loop:
> .L1:
> [r162] <- x
> r162 <- r162 + 4
> ...
> b .L1
>
> After unrolling:
> .L1:
> [r162] <- x
> r197 <- r162 + 4
> r162 <- r197
> ...
> [r162] <- y
> r162 <- r197 + 4
> ...
> b .L
On Fri, Jun 28, 2013 at 6:10 PM, Eric Botcazou wrote:
>> Hi, I have a question about register renaming in rtl loop unroll.
>> For an example loop:
>> .L1:
>> [r162] <- x
>> r162 <- r162 + 4
>> ...
>> b .L1
>>
>> After unrolling:
>> .L1:
>> [r162] <- x
>> r197 <- r162 + 4
>> r162 <-
Accordoing to GCC implementation defined
assigned 0x8000u to signed int should be 0x8000.
If GCC generate abs, abs will saturation or not depend on target ISA.
Then the result of the case won't follow the GCC implementation defined.
Then the result of the marco in
libgcc/soft-fp/op-common
> The problem is auto-inc-dec is weak and can only capture
> post-increment in first part of code, generating even worse code for
> RA:
> .L1:
> r197 <- r162
> [r197++] <- x
> ...
> [r162+4] <- y
> r162 <- r197+0x4
> ...
> b .L1
> Now we have two live registers and it seems hard to el
On Fri, 28 Jun 2013, Shiva Chen wrote:
> Does the abssi2 semantically assume target abs shouldn't do saturation ?
Yes. The semantics of RTL abs are modulo, whereas ss_abs does signed
saturation. Likewise for addition, subtraction and multiplication.
(Some RTL codes have more complicated targ
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