On Mon, Jul 30, 2012 at 5:29 PM, Paulo J. Matos wrote:
> On 26/07/12 15:04, Joseph S. Myers wrote:
>>
>> On Thu, 26 Jul 2012, Paulo J. Matos wrote:
>>
>>> My target has 16bit chars.
>>
>>
>> As I explained before, support for such targets is extremely limited and
>> bitrotten (this applies whether
Hi Richard, Hi DJ,
I am currently unable to build m32c gcc port because the
set_optab_handler function has been deleted:
gcc/config/m32c/m32c.c:1873: undefined reference to `set_optab_handler'
I looked at the code in m32c.c:
static void
m32c_init_libfuncs (void)
{
/*
>
> For the other PR you mentioned, that looks like a register allocation
> regression, that should be addresses in IRA rather than in regcprop.
not sure whether this is a RA regression. Though the two pseudo-regs
are connected by reg-move insn and contains same value afterward,
the two live range
On Tue, Jul 31, 2012 at 4:06 PM, Bin.Cheng wrote:
>>
>> For the other PR you mentioned, that looks like a register allocation
>> regression, that should be addresses in IRA rather than in regcprop.
>
> not sure whether this is a RA regression.
Well, it worked before, and now it doesn't. Maybe RA
On 2012-07-31 03:47, Nick Clifton wrote:
> /* We do this because the M32C has an HImode operand, but the
> M16C has an 8-bit operand. Since gcc looks at the match data
> and not the expanded rtl, we have to reset the optab so that
> the right modes are found. */
>
Hi All
Here at Icron we are using the Leon SPARC CPU in a very minimal setting with no
operating system. We have set the CPU for a large number of register windows,
and have defined register window overflow and underflow traps as fatal
conditions that do not need to be supported. This model o
On 2012-07-31 03:47, Nick Clifton wrote:
> if (TARGET_A24)
> {
> set_optab_handler (cstore_optab, QImode, CODE_FOR_cstoreqi4_24);
> set_optab_handler (cstore_optab, HImode, CODE_FOR_cstorehi4_24);
> set_optab_handler (cstore_optab, PSImode, CODE_FOR_cstor
On Sun, Jul 29, 2012 at 12:48 PM, Perry Smith wrote:
> Hi,
>
> This is an age old topic but I can't find how to solve it. I've searched the
> past few days.
>
> I'm trying to build passenger on AIX 6.1 TL07 SP03 using gcc 4.5.2 that I
> built myself. I've used it for a number of months and hav
>> Though the two pseudo-regs
>> are connected by reg-move insn and contains same value afterward,
>> the two live ranges(i.e. allocnos) are conflict with each other, thus IRA
>> cannot allocate same hard register for them.
>
> If two allocnos have the same value, why can't IRA coalesce them?
I don
