On 01/05/2012 20:11, Joern Rennecke wrote:
Quoting Richard Sandiford :
nick clifton writes:
OK, but what if it turns out that the new algorithm improves the
performance of some benchmarks/applications, but degrades others, within
the same architecture ? If that turns out to be the case (and I
On Tue, May 1, 2012 at 8:36 AM, Ramana Radhakrishnan
wrote:
> Sorry about the delayed response, I've been away for some time.
>
>>
>> I don't exactly understand why the general transform is not advisable.
>> We already synthesize min/max operations.
>
>
>>
>> Can you elaborate on why you think tha
Hello,
In a course at my university (Universität Würzburg, Germany) we have
created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL)
which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far
if we want to do anything with it, we have to write the assembly code
ourselves
On Wed, May 02, 2012 at 01:30:19PM +0200, Ben Morgan wrote:
> In a course at my university (Universität Würzburg, Germany) we have
> created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL)
> which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far
> if we want to do an
On 2 May 2012 10:37, David Brown wrote:
> A second thing that would be hugely convenient for advanced users and
> testers (and people like me who just like to read manuals) would be a
> version number attached to each option, so that we can see which gcc
> versions support it. Some of us use multi
On Wed, 2 May 2012, Ben Morgan wrote:
> Hello,
>
> In a course at my university (Universität Würzburg, Germany) we have
> created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL)
> which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far
> if we want to do anything wi
I am pleased to announce the release of ODB 2.0.0.
ODB is an open source object-relational mapping (ORM) system for C++. It
allows you to persist C++ objects to a relational database without having
to deal with tables, columns, or SQL and without manually writing any of
the mapping code.
ODB is i
Hi,
I have an issue (gcc 4.6.3, private bacakend) when reloading operands of
this insn:
(set (subreg:SI (reg:QI 21 [ iftmp.1 ]) 0)
(lshiftrt:SI (reg/v:SI 24 [ w ]) (const_int 31 [0x1f]))
The register 21 is reloaded into
(reg:QI 0 r0 [orig:21 iftmp.1 ] [21]), which is a HI-wide hw register.
S
On 30/04/12 13:01, Peter Bigot wrote:
I would like to see the technical details, if your code is released somewhere.
Hi Peter,
Sorry for the delay.
The code is not released, however I can send you a patch against GCC
4.6.3 sources (our GCC 4.7.0 port is not yet stable) of our changes and
wi
Hi Richard,
Well, given the replies from you, Ian and Vlad (when reviewing the patch),
I feel once again in a minority of one here :-) but... I just don't
think we should be advertising this sort of stuff to users.
OK, what about Ian's suggestion of controlling the algorithm selection
via a -
Ben Morgan wrote:
> In a course at my university (Universität Würzburg, Germany) we have created
> a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL) which we then
> play onto a FPGA (the Xilinx Spartan-3AN) to use. So far if we want to do
> anything with it, we have to write the assem
Ben Morgan writes:
> In a course at my university (Universität Würzburg, Germany) we have
> created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL)
> which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far
> if we want to do anything with it, we have to write the ass
Aurelien Buhrig writes:
> I have an issue (gcc 4.6.3, private bacakend) when reloading operands of
> this insn:
> (set (subreg:SI (reg:QI 21 [ iftmp.1 ]) 0)
> (lshiftrt:SI (reg/v:SI 24 [ w ]) (const_int 31 [0x1f]))
>
> The register 21 is reloaded into
> (reg:QI 0 r0 [orig:21 iftmp.1 ] [21]),
http://www.youtube.com/watch?feature=player_embedded&v=phjGxHn3uKU
To unsubscribe please send email to unsubscr...@cc.psd-prahova.ro
> Ben Morgan wrote:
>
>> In a course at my university (Universität Würzburg, Germany) we have created
>> a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL) which we then
>> play onto a FPGA (the Xilinx Spartan-3AN) to use. So far if we want to do
>> anything with it, we have to write
Le 02/05/2012 16:41, Ian Lance Taylor a écrit :
> Aurelien Buhrig writes:
>
>> I have an issue (gcc 4.6.3, private bacakend) when reloading operands of
>> this insn:
>> (set (subreg:SI (reg:QI 21 [ iftmp.1 ]) 0)
>> (lshiftrt:SI (reg/v:SI 24 [ w ]) (const_int 31 [0x1f]))
>>
>> The register 21
On Wed, 2 May 2012, Ian Lance Taylor wrote:
> It's worth looking at Anthony Green's blog about implementing moxie at
> http://moxielogic.org/ , as he described the process of doing a full GCC
> port.
Let me clarify that Anthony described porting in his "GGX patch archives",
linked in my other r
On 02/05/12 14:13, nick clifton wrote:
> Hi Richard,
>
>> Well, given the replies from you, Ian and Vlad (when reviewing the patch),
>> I feel once again in a minority of one here :-) but... I just don't
>> think we should be advertising this sort of stuff to users.
>
> OK, what about Ian's sugge
On Fri, Apr 27, 2012 at 9:24 PM, David Sehr wrote:
> Hello All,
>
> We are using gcc trunk as of 4/27/12, and are attempting to add
> support to the ARM gcc compiler for Native Client.
> We are trying to get gcc -march=armv7-a to use movw/movt consistently
> instead of minipools. The motivation is
On Wed, May 2, 2012 at 8:08 AM, Paulo J. Matos wrote:
> On 30/04/12 13:01, Peter Bigot wrote:
>>
>> I would like to see the technical details, if your code is released
>> somewhere.
>>
>
> Hi Peter,
>
> Sorry for the delay.
> The code is not released, however I can send you a patch against GCC 4.6
> I have an issue (gcc 4.6.3, private bacakend) when reloading operands of
> this insn:
> (set (subreg:SI (reg:QI 21 [ iftmp.1 ]) 0)
> (lshiftrt:SI (reg/v:SI 24 [ w ]) (const_int 31 [0x1f]))
>
> The register 21 is reloaded into
> (reg:QI 0 r0 [orig:21 iftmp.1 ] [21]), which is a HI-wide hw reg
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