how to distinguish patched GCCs

2011-05-26 Thread Matthias Kretz
Hi, Abstract :) === A means to distinguish a patched GCC release from a vanilla GCC release should be added. This would enable developers to work around incompatibilities between GCC releases in public header files. One macro, defined only by the respective distrib

Re: how to distinguish patched GCCs

2011-05-26 Thread Richard Guenther
On Thu, May 26, 2011 at 12:06 PM, Matthias Kretz wrote: > Hi, > > Abstract :) > === >     A means to distinguish a patched GCC release from a vanilla GCC >     release should be added.   This would enable developers to work >     around incompatibilities between  GCC releases in public hea

Re: how to distinguish patched GCCs

2011-05-26 Thread Jakub Jelinek
On Thu, May 26, 2011 at 12:06:18PM +0200, Matthias Kretz wrote: > suggested solution > == > GCC should provide (an) additional predefined macro(s) to distinguish a > patched GCC from vanilla GCC. This/These macro(s) should be sufficient to > uniquely identify every released GCC fr

Help with specifying processor pipeline GCC4.5.1

2011-05-26 Thread Rohit Arul Raj
Hello All, I need some help with setting the pipeline hazard recognizer (I am working with gcc v4.5.1 for a private target). A brief pipeline description of my target: We have 2 functional units 1) For multiplication. 2) For All other instructions. a) Multiply instructions are n

Re: Deprecating mips-openbsd

2011-05-26 Thread Andrew Haley
On 05/24/2011 10:40 AM, Andrew Haley wrote: > On 23/05/11 19:35, Richard Sandiford wrote: >> According to: >> >> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47110 >> >> mips-openbsd does not build in 4.6. I haven't seen any activity >> on this port for years. Would anyone object to its deprec

Wrong code: missing input reload

2011-05-26 Thread Georg-Johann Lay
Trying to track faulty code generation because of a missing input reload, I got lost in reload and need some help. The insn to reload (insn 7) is (set (subreg:QI (reg:HI 28) 0) (const_int 0)) This insn generates one output reload (.ira dump) Reloads for insn # 7 Reload 0: reload_out (HI) =

Re: Wrong code: missing input reload

2011-05-26 Thread Georg-Johann Lay
Georg-Johann Lay wrote: > so there is a missing input reload, i.e. prior to insn 7 there must be > something like > > (set (reg:HI 28) > (reg:HI 24)) > Typo, that should read: (set (reg:HI 24) (reg:HI 28)) prior to insn 7.

Re: finding the induction variable after graphite (before ivcanon pass)?

2011-05-26 Thread Alexey Kravets
On 05/24/2011 10:09 PM, Sebastian Pop wrote: One change that I introduced sometime in February is that some reductions are not translated to a zero dim array to make the dependence test work on some of the interchange testcases. With this change, are we going to also create privatized copies for

Re: finding the induction variable after graphite (before ivcanon pass)?

2011-05-26 Thread Sebastian Pop
On Thu, May 26, 2011 at 09:58, Alexey Kravets wrote: > On 05/24/2011 10:09 PM, Sebastian Pop wrote: >> >> One change that I introduced sometime in February is that some reductions >> are not translated to a zero dim array to make the dependence test work >> on some of the interchange testcases.  W

Re: Wrong code: missing input reload

2011-05-26 Thread Richard Henderson
On 05/26/2011 06:53 AM, Georg-Johann Lay wrote: > Trying to track faulty code generation because of a missing input > reload, I got lost in reload and need some help. > > The insn to reload (insn 7) is > > (set (subreg:QI (reg:HI 28) 0) > (const_int 0)) > > This insn generates one output re

Re: [RFC] alpha/ev6: model 1-cycle cross-cluster delay

2011-05-26 Thread Richard Henderson
On 05/24/2011 08:52 PM, Matt Turner wrote: > Alpha EV6 and newer can execute four instructions per cycle if correctly > scheduled. The architecture has two clusters {0, 1}, each with its own > register file. In each cluster, there are two slots {upper, lower}. Some > instructions only execute from

Re: Wrong code: missing input reload

2011-05-26 Thread Eric Botcazou
> Don't see a strict-low-part here. Why do you believe that this > should have an input reload? This is AVR so QImode is the word mode and the strict-low-part is implicit. > Perhaps the original subreg shouldn't have been there? Yes, I'd think that everything in the RTL middle-end expects word-

Re: Wrong code: missing input reload

2011-05-26 Thread Georg-Johann Lay
Eric Botcazou schrieb: Perhaps the original subreg shouldn't have been there? Yes, I'd think that everything in the RTL middle-end expects word-mode subregs of double-word-mode hard regs to be simplifiable. You are right, I was staring at the wrong place. subreg of hardreg should not be th

Re: Wrong code: missing input reload

2011-05-26 Thread Eric Botcazou
> You are right, I was staring at the wrong place. subreg of hardreg > should not be there. You can take a look at PR target/48830, this is a related problem for the SPARC where reload generates: (set (reg:SI 708 [ D.2989+4 ]) (subreg:SI (reg:DI 72 %f40) 4)) and (subreg:SI (reg:DI 72 %f40)

gcc-4.5-20110526 is now available

2011-05-26 Thread gccadmin
Snapshot gcc-4.5-20110526 is now available on ftp://gcc.gnu.org/pub/gcc/snapshots/4.5-20110526/ and on various mirrors, see http://gcc.gnu.org/mirrors.html for details. This snapshot has been generated from the GCC 4.5 SVN branch with the following options: svn://gcc.gnu.org/svn/gcc/branches