David Edelsohn <[EMAIL PROTECTED]> wrote on 02.03.2007 19:10:58:
> > Devang Patel writes:
>
> >> Is there a reason why op0 is V4SF
> Devang> It is destination so, yes this is wrong.
>
> >> and op1 is V4SI (and not V8HI)?
>
> Devang> condition should be v4si, but it is not op1. So this is al
> Devang Patel writes:
>> Is there a reason why op0 is V4SF
Devang> It is destination so, yes this is wrong.
>> and op1 is V4SI (and not V8HI)?
Devang> condition should be v4si, but it is not op1. So this is also not
correct.
>> And also, why not use if_then_else instead of unspec (in all
Is there a reason why op0 is V4SF
It is destination so, yes this is wrong.
and op1 is V4SI (and not V8HI)?
condition should be v4si, but it is not op1. So this is also not correct.
And also, why not use if_then_else instead of unspec (in all vcond's)?
I did not try that path. May be I di
Hi,
We were looking at the implementation of vcond for altivec and we have a
couple of questions.
vcond has 6 operands, rs6000_emit_vector_cond_expr is called from
define_expand for "vcond". It gets those operands in their original
order, as in vcond, and emits op0 = (op4 cond op5 ? op1 : op2),
