> How to tell gcc to insert high, low, and combine operations, when 32
> and 64 bit operations are exchanging values?
CANNOT_CHANGE_MODE_CLASS
Paul
Hi,
My target architecture has 32 bit registers and uses register pairs
for 64 bit values. What makes it special is that whenever a register
pair is written by a 64 bit operation, the individual registers should
not be read by 32 bit operations. The reverse is also true: whenever a
register pair i
Ling-hua Tseng wrote:
(Does (high:SI ...) have the semantic of clearing LSB 16-bit ? )
Storing an SImode value into an SImode reg will set the entire register,
unless you are using subreg/zero_extract/etc on the destination. So
yes, this will clear the low order bits, where the number of
James E Wilson wrote:
Ling-hua Tseng wrote:
It's obvious that `movil' and `movim' are only access the partial
16-bit of the 32-bit register. How can I use RTL expression to
represent the operations?
As you noticed, within a register, subreg can only be used for low
parts. You can't ask for the h
Ling-hua Tseng wrote:
James E Wilson wrote:
I read the descriptions of (high:m exp) and (lo_sum:m x y) in the gcc
internal manuls (Section 10.7 and 10.9).
The last line of their descriptions confused me because they wrote "m
should be Pmode".
A doc bug. You only need Pmode if you are operating o
James E Wilson wrote:
Ling-hua Tseng wrote:
It's obvious that `movil' and `movim' are only access the partial
16-bit of the 32-bit register. How can I use RTL expression to
represent the operations?
As you noticed, within a register, subreg can only be used for low
parts. You can't ask for the h
Ling-hua Tseng wrote:
> It's obvious that `movil' and `movim' are only access the partial
> 16-bit of the 32-bit register. How can I use RTL expression to
> represent the operations?
As you noticed, within a register, subreg can only be used for low
parts. You can't ask for the high part of a s
Hi,
I have been working on very similar issues for the avr target. You might have
a look at the patch I have posted today and the corresponding discussion
thread at the gcc-patches list.
I have also observed, that gen_highpart and gen_lowpart sometimes causes an
ICE for reasons. ... did not f
I have a chip which is developed by other lab.
It's VLIW architecture and it contains 2 RISCs and 8 DSPs.
The size of all registers are 32 bits.
There is a special instruction in the RISC which is called `movi' (move
immediate).
Its syntax and semantic are:
movilr1, # (moves # to LSB 16-bit,
