Hello,
Thanks alot Vladimir and Daniel.
Regards,
Kunal
On Tue, 8 Mar 2005 11:12:46 -0500, Daniel Jacobowitz <[EMAIL PROTECTED]> wrote:
> On Tue, Mar 08, 2005 at 09:38:19PM +0530, Kunal Parmar wrote:
> > Hello,
> > I have attached the dump after the scheduler. The branch instruction
> > is a condi
On Tue, Mar 08, 2005 at 09:38:19PM +0530, Kunal Parmar wrote:
> Hello,
> I have attached the dump after the scheduler. The branch instruction
> is a conditionally executed branch instruction. So it is represented
> as RTL COND_EXEC.
Vladimir was right. It's an INSN, when it should be a JUMP_INSN.
Hello,
I have attached the dump after the scheduler. The branch instruction
is a conditionally executed branch instruction. So it is represented
as RTL COND_EXEC.
Regards,
Kunal
On Tue, 08 Mar 2005 10:14:05 -0500, Vladimir Makarov
<[EMAIL PROTECTED]> wrote:
> Kunal Parmar wrote:
>
> >Following
Kunal Parmar wrote:
Following is the debugging dump by the scheduler -
**
;; ==
;; -- basic block 1 from 17 to 89 -- after reload
;; ==
;;
Hello,
I am working with c6x processor from TI. It has a VLIW architecture.
It has 32 registers namedly a0-a15 and b0-b15. b15 is used as the SP
in the current port.
I am facing a problem with the scheduler of GCC.
Following is the c code I was compiling -
***
int
Hello,
I am working with c6x processor from TI. It has a VLIW architecture.
It has 32 registers namedly a0-a15 and b0-b15. b15 is used as the SP
in the current port.
I am facing a problem with the scheduler of GCC.
Following is the c code I was compiling -
***
int
