age-
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
> Nikolai Bozhenov
> Sent: Monday, September 14, 2015 2:28
> To: James Greenhalgh
> Cc: gcc@gcc.gnu.org
> Subject: Re: [AArch64] A question about Cortex-A57 pipeline description
>
> Thanks for
00, Nikolai Bozhenov wrote:
Hi!
Recently I got somewhat confused by Cortex-A57 pipeline description in
GCC and
I would be grateful if you could help me understand a few unclear points.
Sure,
Particularly I am interested in how memory operations (loads/stores) are
scheduled. It seems that acc
On Fri, Sep 11, 2015 at 04:31:37PM +0100, Nikolai Bozhenov wrote:
> Hi!
>
> Recently I got somewhat confused by Cortex-A57 pipeline description in
> GCC and
> I would be grateful if you could help me understand a few unclear points.
Sure,
> Particularly I am interested in how
Hi!
Recently I got somewhat confused by Cortex-A57 pipeline description in
GCC and
I would be grateful if you could help me understand a few unclear points.
Particularly I am interested in how memory operations (loads/stores) are
scheduled. It seems that according to the cortex-a57.md file
, Alexander Monakov wrote:
> From: Alexander Monakov
> Subject: Re: pipeline description
> To: "Ian Lance Taylor"
> Cc: "roy rosen" , gcc@gcc.gnu.org
> Date: Friday, November 12, 2010, 1:22 PM
>
>
> On Thu, 11 Nov 2010, Ian Lance Taylor wrote:
>
> >
On Thu, 11 Nov 2010, Ian Lance Taylor wrote:
> roy rosen writes:
>
> > If I have two insns:
> > r2 = r3
> > r3 = r4
> > It seems to me that the dependency analysis creates a dependency
> > between the two and prevent parallelization. Although there is a
> > dependency (because of r3) I want GC
roy rosen writes:
> If I have two insns:
> r2 = r3
> r3 = r4
> It seems to me that the dependency analysis creates a dependency
> between the two and prevent parallelization. Although there is a
> dependency (because of r3) I want GCC to parallelize them together.
> Since if the insns are process
sen writes:
>
>> I am writing now the pipeline description in order to get a parallel code.
>> My machine has many restrictions regarding which instruction can be
>> parallelized with another.
>> I am under the assumption that for each insn only one
>> define_insn_reserv
roy rosen writes:
> I am writing now the pipeline description in order to get a parallel code.
> My machine has many restrictions regarding which instruction can be
> parallelized with another.
> I am under the assumption that for each insn only one
> define_insn_reservation i
Hi,
I am writing now the pipeline description in order to get a parallel code.
My machine has many restrictions regarding which instruction can be
parallelized with another.
I am under the assumption that for each insn only one
define_insn_reservation is matched.
Is that correct? If so then the
`condition` for two or more
> different `define_insn_
> reservation` constructors if TRUE for an insn".
>
> While in mips.md, pipeline description for each processor are
> included along with
> generic.md, which providing a fallback for processor without specific
> pipeline des
sn_
reservation` constructors if TRUE for an insn".
While in mips.md, pipeline description for each processor are
included along with
generic.md, which providing a fallback for processor without specific
pipeline description.
Here is the PUZZLE: Won't `define_insn_reservation` constructors
from
H. J. Lu wrote:
If an instruction has latency 3 and throughput 1, should I write it as
(define_insn_reservation "simple" 3
(eq_attr "memory" "none")
"p0")
or
(define_insn_reservation "simple" 3
(eq_attr "memory" "none")
"p0,nothing*2")
Are they equivalent?
Yes.
What happens when ther
If an instruction has latency 3 and throughput 1, should I write it as
(define_insn_reservation "simple" 3
(eq_attr "memory" "none")
"p0")
or
(define_insn_reservation "simple" 3
(eq_attr "memory" "none")
"p0,nothing*2")
Are they equivalent? What happens when there are fewer reservation
Ling-hua Tseng wrote:
> It's only correct if the two RISC insns reserved the same RISC function
> unit.
Try defining two separate reservations for each pipe, e.g. a
risc_data_processing_r0 and a risc_data_processing_r1. Then you can
write the bypass rule in the obvious way.
--
Jim Wilson, GNU To
3, r4@ write back to register at the E4 stage
nop.r0 @ stall 1 cycle
nop.r0 @ stall 1 cycle
nop.r0 @ stall 1 cycle
add.r1r5, r6, r2@ no forwarding mechanism between two different
function units
The pip
16 matches
Mail list logo
