To solve the above issue, can I use the "define_peephole2" insn pattern?
No. At most you could abuse it to hide the issue some of the time.
You probably have one or more of your target macros / hooks wrong,
e.g. HARD_REGNO_NREGS.
Thank you very much for your reply. In my case, code generation
To solve the above issue, can I use the "define_peephole2" insn pattern?
No. At most you could abuse it to hide the issue some of the time.
You probably have one or more of your target macros / hooks wrong,
e.g. HARD_REGNO_NREGS.
Any comments or suggestions most welcome.
read and understand
Hello,
I have ported gcc to a 16-bit target. Now problem is, gcc generates wrong code
with -O1 and above optimization for move and load/store instructions, b using
the 32-bit registers with 16-bit instructions. For ex:
===
move r13, r1 // move 0-15 bit to r1 register
move r13, r0 // move 16-31
