> Then this must be a very dummy question. How the compiler keep the
> instruction order in the RTL IR format in a function? By the information
> like "insn 50 56 51" ? e.g.,
> (insn 50 56 51 4 (clobber (reg/i:SI 0 ax)) -1 (nil) )
It's a linked list. The 56 and 51 link to the previous and nex
sean yang wrote on 05/19/06 15:48:
> can I assume that the final virtual address for
> an instruction in BB_m is always higher than the virtual address for an
> instruction in BB_n, when m < n.
>
No. Think code insertion.
From: Dale Johannesen <[EMAIL PROTECTED]>
To: sean yang <[EMAIL PROTECTED]>
CC: Dale Johannesen <[EMAIL PROTECTED]>, gcc@gcc.gnu.org
Subject: Re: address order and BB numbering
Date: Fri, 19 May 2006 12:54:56 -0700
On May 19, 2006, at 12:48 PM, sean yang wrote:
Although
On May 19, 2006, at 12:48 PM, sean yang wrote:
Although "BASIC_BLOCK array contains BBs in an unspecified order"
as the GCC internal doc says, can I assume that the final virtual
address for an instruction in BB_m is always higher than the
virtual address for an instruction in BB_n, when m
Although "BASIC_BLOCK array contains BBs in an unspecified order" as the GCC
internal doc says, can I assume that the final virtual address for an
instruction in BB_m is always higher than the virtual address for an
instruction in BB_n, when m < n. (Let's assume the linker for the target
machi
