a super regular RISC that encodes constants in immediate blocks

Hi GCC folks, introducing a new RISC instruction set with a variable length instruction packet using a super regular extension scheme with compression techniques to separate the instruction stream into two streams, one for instructions and and one for constants: - latest: https://metaparadigm.co

a super regular RISC that encodes constants in immediate blocks.

Hi Folks, here is an idea expressed as a simple proof-of-concept simulator. - https://github.com/michaeljclark/glyph/ I have been working on a proof-of-concept simulator for a RISC architecture with an immediate base register next to the program counter to split the front-end stream into inde