> Also are you doing pic code or non-pic code? Is your chip a mips clone?
Both pic and non-pic codes are supported. The chip has some features
from arm, such as conditional execution, scaled immediate, pc-relative
branch. I choose mips-elf as start just because we are familiar with
mips and that s
On Feb 13, 2006, at 8:31 PM, Eric Fisher wrote:
Thanks. I'm working to port gcc to our chip. I use mips-elf as the
start.
Most chips have this same issue, you can copy from ppc for example,
or arm, if your chip is more like it (hope not).
we don't have pc-region branch instructions such a
On Feb 13, 2006, at 8:31 PM, Eric Fisher wrote:
Thanks. I'm working to port gcc to our chip. I use mips-elf as the
start. Yet,
we don't have pc-region branch instructions such as 'j target'. So I'm
confused how to solve the function call translation. Thanks again.
If you don't have a jump t
Thanks. I'm working to port gcc to our chip. I use mips-elf as the start. Yet,
we don't have pc-region branch instructions such as 'j target'. So I'm
confused how to solve the function call translation. Thanks again.
Eric.
2006/2/14, Mike Stump <[EMAIL PROTECTED]>:
> On Feb 13, 2006, at 7:28 PM,
On Feb 13, 2006, at 7:28 PM, Eric Fisher wrote:
Suppose I have only pc-relative branch instructions such as 'b offset'
and don't have pc-region branch instructions such as 'j target'. So
what the function call should be translated? Do I have to always use
two instructions such as 'la reg, fun
Hi,
Happy Valentine's Day.
Suppose I have only pc-relative branch instructions such as 'b offset'
and don't have pc-region branch instructions such as 'j target'. So
what the function call should be translated? Do I have to always use
two instructions such as 'la reg, func' and 'b reg'? Especially
