2016-04-18 10:33 GMT+01:00 Richard Biener :
> On Mon, Apr 11, 2016 at 1:54 PM, Ilya Enkovich wrote:
>> 2016-04-10 3:34 GMT+03:00 David Guillen Fandos :
>>> On 07/04/16 09:09, Ilya Enkovich wrote:
2016-04-07 0:49 GMT+03:00 David Guillen Fandos :
>
> Thanks a lot Ilya!
>
> I man
On Mon, Apr 11, 2016 at 1:54 PM, Ilya Enkovich wrote:
> 2016-04-10 3:34 GMT+03:00 David Guillen Fandos :
>> On 07/04/16 09:09, Ilya Enkovich wrote:
>>> 2016-04-07 0:49 GMT+03:00 David Guillen Fandos :
Thanks a lot Ilya!
I managed to get it working. There were some bugs regardin
2016-04-10 3:34 GMT+03:00 David Guillen Fandos :
> On 07/04/16 09:09, Ilya Enkovich wrote:
>> 2016-04-07 0:49 GMT+03:00 David Guillen Fandos :
>>>
>>> Thanks a lot Ilya!
>>>
>>> I managed to get it working. There were some bugs regarding register
>>> allocation that ended up promoting the class to
On 07/04/16 09:09, Ilya Enkovich wrote:
> 2016-04-07 0:49 GMT+03:00 David Guillen Fandos :
>>
>> Thanks a lot Ilya!
>>
>> I managed to get it working. There were some bugs regarding register
>> allocation that ended up promoting the class to be BLKmode instead of
>> V4SFmode. I had to debug it a bi
2016-04-07 0:49 GMT+03:00 David Guillen Fandos :
>
> Thanks a lot Ilya!
>
> I managed to get it working. There were some bugs regarding register
> allocation that ended up promoting the class to be BLKmode instead of
> V4SFmode. I had to debug it a bit, which is tricky, but in the end I
> found my
On 06/04/16 10:44, Ilya Enkovich wrote:
> 2016-04-06 1:50 GMT+03:00 David Guillen Fandos :
>>
>> Thanks again Ilya,
>>
>> That seems to help to solve the problem. Now I'm facing another issue.
>> It seems the tree-vec-generic pass is promoting my vector operations to
>> BLKmode and therefore the VE
2016-04-06 1:50 GMT+03:00 David Guillen Fandos :
>
> Thanks again Ilya,
>
> That seems to help to solve the problem. Now I'm facing another issue.
> It seems the tree-vec-generic pass is promoting my vector operations to
> BLKmode and therefore the VECTOR_MODE_P macro evaluates to false,
> falling
On 05/04/16 09:13, Ilya Enkovich wrote:
> 2016-04-05 1:59 GMT+03:00 David Guillen Fandos :
>>
>>
>> On 04/04/16 10:55, Ilya Enkovich wrote:
>>> 2016-04-02 3:32 GMT+03:00 David Guillen Fandos :
Hello there!
I'm trying to add some vector registers to a MIPS arch (32 bit). This
a
2016-04-05 1:59 GMT+03:00 David Guillen Fandos :
>
>
> On 04/04/16 10:55, Ilya Enkovich wrote:
>> 2016-04-02 3:32 GMT+03:00 David Guillen Fandos :
>>> Hello there!
>>>
>>> I'm trying to add some vector registers to a MIPS arch (32 bit). This
>>> arch has 32 x 128 bit registers that can essentially
On 04/04/16 10:55, Ilya Enkovich wrote:
> 2016-04-02 3:32 GMT+03:00 David Guillen Fandos :
>> Hello there!
>>
>> I'm trying to add some vector registers to a MIPS arch (32 bit). This
>> arch has 32 x 128 bit registers that can essentially be seen as V4SF.
>> So far I'm using this test:
>>
>> vola
2016-04-02 3:32 GMT+03:00 David Guillen Fandos :
> Hello there!
>
> I'm trying to add some vector registers to a MIPS arch (32 bit). This
> arch has 32 x 128 bit registers that can essentially be seen as V4SF.
> So far I'm using this test:
>
> volatile float foo __attribute__ ((vector_size (16)));
Hello there!
I'm trying to add some vector registers to a MIPS arch (32 bit). This
arch has 32 x 128 bit registers that can essentially be seen as V4SF.
So far I'm using this test:
volatile float foo __attribute__ ((vector_size (16)));
volatile float bar __attribute__ ((vector_size (16)));
int m
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