On 08/03/16 19:11, Jeff Law wrote:
On 03/08/2016 11:49 AM, Richard Henderson wrote:
On 03/07/2016 02:49 PM, Jeff Law wrote:
On 03/07/2016 03:44 AM, Kyrill Tkachov wrote:
The RTL documentation for ASHIFT and friends says that the shift amount
must be:
"a fixed-point mode or be a constant wi
On 03/08/2016 11:49 AM, Richard Henderson wrote:
On 03/07/2016 02:49 PM, Jeff Law wrote:
On 03/07/2016 03:44 AM, Kyrill Tkachov wrote:
The RTL documentation for ASHIFT and friends says that the shift amount
must be:
"a fixed-point mode or be a constant with mode @code{VOIDmode}; which
mode i
On 03/07/2016 02:49 PM, Jeff Law wrote:
On 03/07/2016 03:44 AM, Kyrill Tkachov wrote:
The RTL documentation for ASHIFT and friends says that the shift amount
must be:
"a fixed-point mode or be a constant with mode @code{VOIDmode}; which
mode is determined by the mode called for in the machine
On 03/07/2016 03:44 AM, Kyrill Tkachov wrote:
The RTL documentation for ASHIFT and friends says that the shift amount
must be:
"a fixed-point mode or be a constant with mode @code{VOIDmode}; which
mode is determined by the mode called for in the machine description
entry for the left-shift ins
Kyrill Tkachov writes:
> On 05/03/16 05:52, Jeff Law wrote:
>> On 03/04/2016 09:33 AM, Kyrill Tkachov wrote:
>>>
>>> On 04/03/16 16:21, Jeff Law wrote:
On 03/04/2016 08:05 AM, Richard Biener wrote:
>> does that mean that the shift amount should be DImode?
>> Seems like a more flexible
On 05/03/16 05:52, Jeff Law wrote:
On 03/04/2016 09:33 AM, Kyrill Tkachov wrote:
On 04/03/16 16:21, Jeff Law wrote:
On 03/04/2016 08:05 AM, Richard Biener wrote:
does that mean that the shift amount should be DImode?
Seems like a more flexible approach would be for the midend to be able
to h
On 03/04/2016 09:33 AM, Kyrill Tkachov wrote:
On 04/03/16 16:21, Jeff Law wrote:
On 03/04/2016 08:05 AM, Richard Biener wrote:
does that mean that the shift amount should be DImode?
Seems like a more flexible approach would be for the midend to be able
to handle these things...
Or macroize f
On 04/03/16 16:21, Jeff Law wrote:
On 03/04/2016 08:05 AM, Richard Biener wrote:
does that mean that the shift amount should be DImode?
Seems like a more flexible approach would be for the midend to be able
to handle these things...
Or macroize for all integer modes?
That's probably worth ex
On 03/04/2016 08:05 AM, Richard Biener wrote:
does that mean that the shift amount should be DImode?
Seems like a more flexible approach would be for the midend to be able
to handle these things...
Or macroize for all integer modes?
That's probably worth exploring. I wouldn't be at all surpris
On 04/03/16 15:12, Kyrill Tkachov wrote:
On 04/03/16 15:07, Segher Boessenkool wrote:
On Fri, Mar 04, 2016 at 02:48:21PM +, Kyrill Tkachov wrote:
Although there are case where we hit the same problem:
unsigned long
f3 (unsigned long bit_addr)
{
unsigned long bitnumb = bit_addr & 63;
On 04/03/16 15:07, Segher Boessenkool wrote:
On Fri, Mar 04, 2016 at 02:48:21PM +, Kyrill Tkachov wrote:
Although there are case where we hit the same problem:
unsigned long
f3 (unsigned long bit_addr)
{
unsigned long bitnumb = bit_addr & 63;
return (1L << bitnumb);
}
combine will tr
On Fri, Mar 04, 2016 at 02:48:21PM +, Kyrill Tkachov wrote:
> Although there are case where we hit the same problem:
> unsigned long
> f3 (unsigned long bit_addr)
> {
> unsigned long bitnumb = bit_addr & 63;
> return (1L << bitnumb);
> }
>
> combine will try to match:
> (set (reg:DI 78)
>
On March 4, 2016 3:48:21 PM GMT+01:00, Kyrill Tkachov
wrote:
>
>On 04/03/16 14:41, Kyrill Tkachov wrote:
>>
>> On 04/03/16 11:59, Segher Boessenkool wrote:
>>> On Mon, Feb 29, 2016 at 10:51:24AM +, Kyrill Tkachov wrote:
So I'm trying to create a define_insn to match something like:
On 04/03/16 14:41, Kyrill Tkachov wrote:
On 04/03/16 11:59, Segher Boessenkool wrote:
On Mon, Feb 29, 2016 at 10:51:24AM +, Kyrill Tkachov wrote:
So I'm trying to create a define_insn to match something like:
[(set (match_operand:SI 0 "register_operand" "=r")
(ashift:SI
(ma
On 04/03/16 11:59, Segher Boessenkool wrote:
On Mon, Feb 29, 2016 at 10:51:24AM +, Kyrill Tkachov wrote:
So I'm trying to create a define_insn to match something like:
[(set (match_operand:SI 0 "register_operand" "=r")
(ashift:SI
(match_operand:SI 1 "register_operand" "r")
On Mon, Feb 29, 2016 at 10:51:24AM +, Kyrill Tkachov wrote:
> So I'm trying to create a define_insn to match something like:
> [(set (match_operand:SI 0 "register_operand" "=r")
> (ashift:SI
> (match_operand:SI 1 "register_operand" "r")
> (and:QI
> (match_operand:QI 2
Hi Jeff,
On 26/02/16 21:24, Jeff Law wrote:
On 02/26/2016 06:40 AM, Kyrill Tkachov wrote:
Hi all,
I'm looking at a case where some RTL passes create an RTL expression of
the form:
(subreg:QI (and:SI (reg:SI x1)
(const_int 31)) 0)
which I'd like to simplify to:
(and:QI (subreg:QI
On 02/26/2016 06:40 AM, Kyrill Tkachov wrote:
Hi all,
I'm looking at a case where some RTL passes create an RTL expression of
the form:
(subreg:QI (and:SI (reg:SI x1)
(const_int 31)) 0)
which I'd like to simplify to:
(and:QI (subreg:QI (reg:SI x1) 0)
(const_int 31))
I can
Hi all,
I'm looking at a case where some RTL passes create an RTL expression of the
form:
(subreg:QI (and:SI (reg:SI x1)
(const_int 31)) 0)
which I'd like to simplify to:
(and:QI (subreg:QI (reg:SI x1) 0)
(const_int 31))
Because (const_int 31) masks out the upper bits after
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